User guide

7–4 Chapter 7: Custom PHY IP Core
Parameter Settings
Altera Transceiver PHY IP Core User Guide December 2010 Altera Corporation
Figure 7–3 shows the top-level interfaces when you disable Avalon data interfaces.
8B/10B Encoder and Decoder
The 8B/10B encoder generates 10-bit code groups (control or data word) with proper
disparity from the 8-bit data and 1-bit control identifier. The 8B/10B decoder receives
10-bit data from the rate matcher and decodes it into an 8-bit data + 1-bit control
identifier. Table 7–3 lists the settings available on the 8B/10B tab.
Figure 7–3. Custom PHY with Avalon Interfaces Enabled
Table 7–3. 8B/10B Options
Name Value Description
Enable 8B/10B decoder/encoder On/Off
Enable this option if your application requires 8B/10B encoding and
decoding. This option on adds the
tx_datak <n>, rx_datak <n>,
and
rx_runningdisp <n> signals to your transceiver.
Enable manual disparity control On/Off
When enabled, you can use the
tx_forcedisp signal to control the
disparity of the 8B/10B encoder. Turning this option on adds the
tx_forcedisp and tx_dispval signals to your transceiver.
Create optional 8B/10B status
port
On/Off
Enable this option on to include additional 8B/10B the
rx_errdetect and rx_disperr error signals at the top level of the
Custom PHY IP core.