User guide
Chapter 7: Custom PHY IP Core 7–7
Parameter Settings
December 2010 Altera Corporation Altera Transceiver PHY IP Core User Guide
If you enable the rate match FIFO, the parameter editor provides options to enter the
rate match insertion and deletion patterns. The lower 10 bits are the control pattern,
and the upper 10 bits are the skip pattern. Table 7–6 lists the settings available on the
Rate Match tab.
Byte Ordering
The byte ordering block is available when the PCS width is doubled at the byte
deserializer. Byte ordering identifies the first byte of a packet by determining whether
the programmed start-of-packet (SOP) pattern is present; it inserts enough pad
characters in the data stream to force the SOP to the lowest order byte lane. Table 7–7
describes the byte order options.
1 You cannot enable Rate Match FIFO when your application requires byte ordering.
Because the rate match function inserts and deletes idle characters, it may shift the
SOP to a different byte lane.
Table 7–6. Rate Match FIFO Options (Note 1)
Name Value Description
Enable rate match FIFO On/Off
Turn this option on, to enable the rate match functionality. Turning
this option on adds the
rx_rmfifofull
,
rxrmfifoempty
,
rxrmfifodatainserted
, and
rx_rmfifodatadeleted
status
signals to your PHY.
Rate match
insertion/deletion +ve
disparity pattern
1101000011
1010000011
Enter a 10-bit skip pattern (bits 10–19) and a 10-bit control pattern
(bits 0–9). The skip pattern must have neutral disparity.
Rate match
insertion/deletion -ve
disparity pattern
0010111100
0101111100
Enter a 10-bit skip pattern (bits 10–19) and a 10-bit control pattern
(bits 0–9). The skip pattern must have neutral disparity.
Note to Table 7–6:
(1) The rate match FIFO is not supported in Stratix V devices.
Table 7–7. Byte Order Options
Name Value Description
Enable byte ordering block On/Off
Turn this option on if your application uses serialization to create a
datapath that is larger than 1 symbol. This option is only available if
you use the byte deserializer.
Enable byte ordering block
manual control
On/Off
Turn this option on to choose manual control of byte ordering. This
option creates the
rx_enabyteord
signal. A byte ordering operation
occurs whenever
rx_enabyteord
is asserted. To perform multiple
byte ordering operations, deassert and reassert
rx_enabyteord
.
Byte ordering pattern
11111011
Specifies the pattern that identifies the SOP.
Byte ordering pad pattern
00000000
Specifies the pad pattern that is inserted to align the SOP.