User guide

7–8 Chapter 7: Custom PHY IP Core
Interfaces
Altera Transceiver PHY IP Core User Guide December 2010 Altera Corporation
Table 7–8 lists the Datapath options.
f For a description of the Analog options, refer the to “PMA Analog Options” on
page 8–4.
Interfaces
Figure 7–4 illustrates the top-level signals of the Custom PHY IP core.
Table 7–8. Datapath Options
Name Value Description
Deserializer block width
Auto
Single
Double
Specifies the mode of operation for the deserializer which clocks in
serial input data from the RX buffer using the high-speed recovered
clock and deserializes it using the low-speed parallel recovered clock.
Forwards deserialized data to the RX PCS channel. The following 3
modes are supported:
■ Auto—Instructs the Quartus II software to determine the
appropriate width
■ Single—supports 8- and 10-bit deserialization factors
■ Double—supports 16- and 20-bit deserialization factors
Deserializer actual width
Auto
Single
Double
Specifies the mode selected.
Figure 7–4. Custom PHY Top-Level Signals (Note 1)
Note to Figure7–4:
(1) <n> is the number of lanes. <d> is the deserialization factor. <s> is the symbol size in bits. <p> is the number of PLLs.
tx_parallel_data[<n><d>-1>:0]
tx_clkout<n>
tx_datak[<n><d>-1:0]
tx_forcedisp[<n><d>-1:0]
tx_dispval[<n><d>-1:0]
rx_parallel_data[<n><d>-1:0]
rx_clkout<n>
rx_datak[<n><d>-1:0]
rx_runningdisp[<n><d>-1:0]
rx_enabyteord[<n>-1:0]
phy_mgmt_clk
phy_mgmt_clk_reset
phy_mgmt_address[8:0]
phy_mgmt_writedata[31:0]
phy_mgmt_readdata[31:0]
phy_mgmt_write
phy_mgmt_read
pll_ref_clk
cal_blk_clk
rx_coreclkin<n>
tx_coreclkin<n>
Custom PHY Top-Level Signals
tx_serial_data<n>
rx_serial_data<n>
tx_ready
rx_ready
pll_locked[<p>-1:0]
tx_forceelecidle[<n>-1:0]
tx_bitslipboundaryselect[<n>4:0]
rx_disperr[<n>/<d>-1:0]
rx_errdetect[<n>/<d>-1:0]
rx_synccstatus[<n>/<d>-1:0]
rx_is_lockedtoref[<n>-1:0]
rx_is_lockedtodata[<n>-1:0]
rx_signaldetect[<n>-1:0]
rx_bitslip
rx_bitsilpboundaryselectout[<n>4:0]
reconfig_togxb[3:0]
reconfig_fromgxb[16:0]
Avalon-ST Tx
from MAC
High Speed
Serial I/O
Avalon-MM PHY
Management
Interface
Clocks
Optional
Optional
Optional
Status
Optional
Avalon-ST Rx
to MAC
Transceiver
Reconfiguration
Interface
Optional