User guide

Chapter 7: Custom PHY IP Core 7–9
Interfaces
December 2010 Altera Corporation Altera Transceiver PHY IP Core User Guide
1 The block diagram shown in the GUI labels the external pins with the interface type
and places the interface name inside the box. The interface type and name are used in
the _hw.tcl.
f For more information about _hw.tcl files, refer to Component Interface Tcl Reference
chapter in the SOPC Builder User Guide.
The following sections describe the signals in each interface.
Avalon-ST TX Input Data from the MAC
Table 7–9 describes the signals in the Avalon-ST input interface. These signals are
driven from the MAC to the PCS. This is an Avalon sink interface.
f For more information about the Avalon-ST protocol, including timing diagrams, refer
to the Avalon Interface Specifications.
Avalon-ST RX Output Data to the MAC
Table 7–10 describes the signals in the Avalon-ST output interface. These signals are
driven from the PCS to the MAC. This is an Avalon source interface.
Table 7–9. Avalon-ST TX Interface
Signal Name Direction Description
tx_parallel_data<n>[<d>-1:0] Sink
This is TX parallel data driven from the MAC. The ready latency on this
interface is 0, so that the PHY must be able to accept data as soon as it
comes out of reset.
tx_clkout Output This is the clock for TX parallel data, control, and status signals.
tx_datak<n> Sink
Data and control indicator for the received data. When 0, indicates that
tx_data is data, when 1, indicates that tx_data is control.
tx_forcedisp Sink
When asserted, this control signal enables disparity to be forced on the
TX channel. This signal is created if you turn On the Enable manual
disparity control option on the 8B/10B tab.
tx_dispval Sink
This control signal specifies the disparity of the data. This port is
created if you turn On the Enable disparity control option on the
8B/10B tab.
Table 7–10. Avalon-ST RX Interface (Part 1 of 2)
Signal Name Direction Description
rx_parallel_data[<n><d>-1:0] Source
This is RX parallel data driven from the Custom PHY IP core. The ready
latency on this interface is 0, so that the MAC must be able to accept
data as soon as the PHY comes out of reset. Data driven from this
interface is always valid.
rx_clkout Output This is the clock for the RX parallel data source interface.
rx_datak < n > Source
Data and control indicator for the source data. When 0, indicates that
rx_parallel_data is data, when 1, indicates that
rx_parallel_data is control.