User guide

7–10 Chapter 7: Custom PHY IP Core
Interfaces
Altera Transceiver PHY IP Core User Guide December 2010 Altera Corporation
Avalon-MM PHY Management Interface
The Avalon-MM PHY management module includes master and slave interfaces. This
component acts as a bridge. It transfers commands received on its Avalon-MM slave
interface to its Avalon-MM master port. This interface provides access to control and
status information for the PCS, PMA, and Reconfiguration blocks.
Figure 7–5 illustrates the role of the PHY Management module in the Custom PHY.
rx_runningdisp Source This status signal indicates the disparity of the incoming data.
rx_enabyteord Input
This signal is created if you turn On the Enable byte ordering block
control option on the Byte Order tab. A byte ordering operation occurs
whenever
rx_enabyteord is asserted. To perform multiple byte
ordering operations, deassert and reassert
rx_enabyteord .
Table 7–10. Avalon-ST RX Interface (Part 2 of 2)
Signal Name Direction Description
Figure 7–5. Custom PHY IP Core (Note 1)
Note to Figure7–5:
(1) Blocks in gray are soft logic. Blocks in white are hard logic.
System
Interconnect
Fabric
System
Interconnect
Fabric
Custom PHY PCS and PMA
Custom PHY IP Core
Dynamic
Partial
Reconfiguration
Resets
Status
Control
S
Avalon-MM
Control
S
Avalon-MM
Status
S
Transceiver
Reconfiguration
Controller
Reset
Controller
Reset
Clocks Clocks
Tx Data Tx Parallel Data
Rx Data Rx Parallel Data
M
Avalon-MM
PHY
Mgmt
S
Rx Serial Data & Status
Tx Serial Data