User guide

Chapter 7: Custom PHY IP Core 7–11
Interfaces
December 2010 Altera Corporation Altera Transceiver PHY IP Core User Guide
PHY Management Signals
Table 7–11 describes the signals in the PHY Management interface.
Register Descriptions
Table 7–12 specifies the registers that you can access over the PHY management
interface using word addresses and a 32-bit embedded processor. A single address
space provides access to all registers.
Table 7–11. Avalon-MM PHY Management Interface
Signal Name Direction Description
phy_mgmt_clk Input
Avalon-MM clock input. The frequency range for the
phy_mgmt_clk varies for different devices, as follows:
■ Arria II GX, Arria II GZ, HardCopy IV GX, and Stratix IV GX
devices: 37.5–125 MHz
■ Stratix V devices: 50–150 MHz
phy_mgmt_clk_reset Input Global reset signal. A positive edge on this signal triggers a reset.
phy_mgmt_address[8:0] Input 9-bit Avalon-MM address.
phy_mgmt_writedata[31:0] Input Input data.
phy_mgmt_readdata[31:0] Output Output data.
phy_mgmt_write Input Write signal.
phy_mgmt_read Input Read signal.
Table 7–12. Low Latency PHY IP Core Registers (Part 1 of 3)
Word
Addr
Bits R/W Register Name Description
PMA Common Control and Status Registers
0x021 [31:0] RW
cal_blk_powerdown
Writing a 1 to channel < n > powers down the calibration
block for channel <
n >.
0x022 [31:0] R
pma_tx_pll_is_locked
Bit[P] indicates that the TX/CMU PLL (P) is locked to the
input reference clock. There is typically one
pma_tx_pll_is_locked bit per system.
Reset Control Registers
0x041 [31:0] RW
reset_ch_bitmask
Reset controller channel bitmask for digital resets. The
default value is all 1s. Channel <
n > can be reset when
<
n > = 1.
0x042 [1:0]
W
reset_control (write)
Writing a 1 to bit 0 initiates a TX digital reset using the reset
controller module. The reset affects channels enabled in the
reset_ch_bitmask. Writing a 1 to bit 1 initiates a RX
digital reset of channels enabled in the
reset_ch_bitmask.
R
reset_status (read)
Reading bit 0 returns the status of the reset controller TX
ready bit. Reading bit 1 returns the status of the reset
controller RX ready bit.