User guide

Chapter 7: Custom PHY IP Core 7–13
Interfaces
December 2010 Altera Corporation Altera Transceiver PHY IP Core User Guide
Clock Interface
Table 7–13 describes optional and required clocks for the Custom PHY. The input
reference clock,
pll_ref_clk , drives a PLL inside the PHY-layer block, and a PLL
output clock,
rx_clkout (described in Table 7–10 on page 7–9) is used for all data,
command, and status inputs and outputs.
0x082
[31:1] R
pcs8g_tx_status Reserved.
[0] RW
tx_phase_comp_fifo_error
When set, indicates an TX phase compensation FIFO error.
From block: TX phase Compensation FIFO
0x083
[31:6] RW
pcs8g_tx_control Reserved.
[0] RW
tx_invpolarity
When set, the TX interface inverts the polarity of the TX
data.
To block: 8B/10B encoder.
[5:1] RW
tx_bitslipboundary_select
Sets the number of bits that the TX bit slipper needs to slip.
To block: Word aligner.
0x084
[31:1] RW Reserved. —
[0] RW
rx_invpolarity
When set, the RX channels inverts the polarity of the
received data.
To block: 8B/10B decoder.
0x085
[31:4] RW
pcs8g_rx_wa_control Reserved.
[0] RW
rx_enapatternalign
When set in manual word alignment mode, the word
alignment logic begins operation when this pattern is set.
To block: Word aligner.
[1] RW
rx_bitreversal_enable
When set, enables bit reversal on the RX interface.
To block: Word aligner.
[2] RW
rx_bytereversal_enable
When set, enables byte reversal on the RX interface.
To block: Byte deserializer.
[3] RW
rx_bitslip
Every time this register transitions from 0 to 1, the RX data
slips a single bit.
To block: Word aligner.
Table 7–12. Low Latency PHY IP Core Registers (Part 3 of 3)
Word
Addr
Bits R/W Register Name Description
Table 7–13. Clock Signals
Signal Name Direction Description
pll_ref_clk Input
Reference clock for the PHY PLLs. Frequency range is
50–700 MHz.
rx_coreclkin Input This is an optional clock to drive the coreclk of the RX PCS.
tx_coreclkin Input This is an optional clock to drive the coreclk of the TX PCS
pipe_pclk Output Clock for TX and RX parallel data, control, and status.