User guide

7–14 Chapter 7: Custom PHY IP Core
Interfaces
Altera Transceiver PHY IP Core User Guide December 2010 Altera Corporation
Transceiver Serial Data Interface
Table 7–14 describes the differential serial data interface and the status signals for the
RX interface.
Optional Status Signals
Table 7–15 describes the optional status signals for the RX interface.
Table 7–14. Serial Interface and Status Signals (Note 1)
Signal Name Direction Signal Name
rx_serial_data[ <n> -1:0] Input Receiver differential serial input data.
tx_serial_data[ <n> -1:0] Output Transmitter differential serial output data.
Note to Table 7–14:
(1) <n> is the number of lanes. <d> is the deserialization factor. <s> is the symbol size in bits. <p> is the number of PLLs.
Table 7–15. Serial Interface and Status Signals (Part 1 of 2) (Note 1)
Signal Name Direction Signal Name
tx_ready Output
When asserted, indicates that the TX interface is ready to
transmit.
rx_ready Output When asserted, indicates that the RX interface is ready to receive.
pll_locked[<p>-1:0] Output
When asserted, indicates that the PLL is locked to the input
reference clock.
tx_forceelecidle[<n>-1:0] Input
When asserted, enables a circuit to detect a downstream receiver.
It is used for the PCI Express protocol.
tx_bitslipboundaryselect
[<n>4:0]
Input
This signal is used for bit slip word alignment mode. It selects the
number of bits that the TX block must slip to achieve a
deterministic latency.
rx_disperr[<d/s><n>-1:0] Output
When asserted, indicates that the received 10-bit code or data
group has a disparity error.
rx_errdetect[<d/s><n>-1:0] Output
When asserted, indicates that a received 10-bit code group has
an 8B/10B code violation or disparity error.
rx_syncstatus[<d/s><n>-1:0] Output
Indicates presence or absence of synchronization on the RX
interface. Asserted when word aligner identifies the word
alignment pattern or synchronization code groups in the received
data stream. This signal is optional.
rx_is_lockedtoref[<n>-1:0] Output
Asserted when the receiver CDR is locked to the input reference
clock. This signal is asynchronous. This signal is optional.
rx_is_lockedtodata[<n>-1:0] Output
When asserted, the receiver CDR is in to lock-to-data mode.
When deasserted, the receiver CDR lock mode depends on the
rx_locktorefclk signal level. This signal is optional.
rx_signaldetect[<n>-1:0] Output
Signal threshold detect indicator required for the PCI Express
protocol. When assertied, it indicates that the signal present at
the receiver input buffer is above the programmed signal
detection threshold value.
rx_bitslip Input
Used for manual control of bit silpping. The word aligner slips a
bit of the current word for every rising edge of this signal.