User guide

Chapter 7: Custom PHY IP Core 7–15
Interfaces
December 2010 Altera Corporation Altera Transceiver PHY IP Core User Guide
Dynamic Partial Reconfiguration I/O Interface
As silicon progresses towards smaller process nodes, circuit performance is affected
more by variations due to process, voltage, and temperature. These process variations
result in analog voltages that can be offset from required ranges. The calibration
performed by the dynamic reconfiguration interface compensates for variations due
to process, voltage and temperature. Table 7–16 describes the signals in the
reconfiguration interface. This interface uses the Avalon-MM PHY Management
interface clock.
rx_bitslipboundaryselectout
[<n>-1:0]
Output
This signal is used for bit slip word alignment mode. It reports
the number of bits that the RX block slipped to achieve a
deterministic latency.
Note to Table 7–14:
(1) <n> is the number of lanes. <d> is the deserialization factor. <s> is the symbol size in bits. <p> is the number of PLLs.
Table 7–15. Serial Interface and Status Signals (Part 2 of 2) (Note 1)
Signal Name Direction Signal Name
Table 7–16. Reconfiguration Interface
Signal Name Direction Description
reconfig_togxb [3:0] Sink
Reconfiguration signals from the Transceiver Reconfiguration
Controller.
reconfig_fromgxb [16:0] Source Reconfiguration signals to the Transceiver Reconfiguration Controller.