User guide

December 2010 Altera Corporation Altera Transceiver PHY IP Core User Guide
8. Low Latency PHY IP Core
The Altera Low Latency IP core receives and transmits differential serial data,
recovering the RX clock from the RX input stream. The PMA connects to a simplified
PCS that whose single function doubles the width of the TX and RX datapaths. An
Avalon-ST interface is used for TX and RX data for the MAC interface. An
Avalon-MM interface provides access to control and status information.
Figure 8–1 illustrates the top-level modules of the Low Latency PHY IP core.
Because the Low latency PHY IP core bypasses much of the standard PCS, it
minimizes the PCS latency. Table 8–1 the compares the latency of the standard and
low latency PCS.
f For more detailed information about the Low Latency datapath and clocking, refer to
the “Standard PCS Custom and Low Latency Configurations” section in the Custom
Transceiver Configuration Datapath in Stratix V Devices chapter of the Stratix V Device
Handbook.
f For more information about the Avalon-MM and Avalon-ST protocols, including
timing diagrams, refer to the Avalon Interface Specifications.
Figure 8–1. Low-Latency PHY IP Core—Stratix IV and Stratix V Devices
Table 8–1. TX Datapath Latency (Note 1)
Block Normal Latency Low Latency
TX Channel
TX Phase Compensation FIFO 4–5 3–5
Byte Serializer 1–2 0–2 (2)
RX Channel
Word Aligner 3–7 (3) 1
Byte Serializer 1–2 1
Byte Ordering 1–3 0
RX Phase Compensation FIFO 3–4 2–3
Notes to Table 8–1:
(1) These numbers are preliminary, pending device characterization.
(2) This value depends on whether the block is enabled or disabled.
(3) This value depends on the configuration mode.
Tx serial data
Rx serial data
Stratix IV or Stratix V FPGA
PMA
PCS
Phase Comp
Byte Serializer
Avalon-MM
Control & Status
Avalon-ST
to
MAC
to
Embedded
Controller