User guide
8–2 Chapter 8: Low Latency PHY IP Core
Device Family Support
Altera Transceiver PHY IP Core User Guide December 2010 Altera Corporation
Device Family Support
IP cores provide either final or preliminary support for target Altera device families.
These terms have the following definitions:
■ Final support—Verified with final timing models for this device.
■ Preliminary support—Verified with preliminary timing models for this device.
Table 8–1 shows the level of support offered by the PMA IP core for Altera device
families.
Performance and Resource Utilization
Accurate resource utilization numbers are not available at this time.
Parameter Settings
To configure the Low Latency PHY IP core in the parameter editor, click Installed
Plug-Ins > Interfaces > Transceiver PHY > Low Latency PHY v10.1.
Table 8–2 lists the settings available on General Options tab.
Table 8–1. Device Family Support
Device Family Support
Stratix V devices Preliminary
Other device families No support.
Table 8–2. General Options
Name Value Description
Device family Stratix V
This IP core is only available Stratix V. Arria II GX, Arria II GZ,
HardCopy IV GX, and Stratix IV GX devices are not supported in
this release.
Number of lanes
1
-
32
Number of channels, default value is 1. For Stratix V devices, the
valid range is 1–24 for the non-bonded mode and 1–5 for the
bonded mode.
Mode of operation
Duplex
RX
TX
Specifies the mode of operation as Duplex, RX, or TX mode.
Phase compensation FIFO mode
None
Embedded
When you select Embedded the PCS includes the phase
compensation FIFO and byte serializer, if required, to double the
data width. Default is None.
Serialization factor
8, 10, 16, 20, 32,
40, 50, 64, 66
This option indicates the parallel data interface width. The
maximum width for Stratix IV devices is 40 bits. The 64- and
66-bit options are not available in the current release.
Data rate
600–12500
Mbps
Specifies the data rate in Mbps. If you choose Bonded mode on
the Additional Options tab, the maximum data rate is 800 Mbps.
Input clock frequency
60–700 MHz
TX PLL input reference frequency in MHz. The allowed range
depends on the device you choose.