User guide

Chapter 8: Low Latency PHY IP Core 8–5
Interfaces
December 2010 Altera Corporation Altera Transceiver PHY IP Core User Guide
Interfaces
Figure 8–2 illustrates the top-level signals of the Low Latency PHY IP core.
RX termination resistance
OCT_85_OHMS
OCT_100_OHMS
OCT_120_OHMS
OCT_150_OHMS
Indicates the value of the termination resistor for the receiver.
Receiver DC gain 0–4
Sets the equalization DC gain using one of the following settings:
■ 0–0 dB
■ 1–3 dB
■ 2–6 dB
■ 3–9 dB
■ 4–12 dB
Receiver static equalizer setting: 0–15
This option sets the equalizer control settings. The equalizer uses a
pass band filter. Specifying a low value passes low frequencies.
Specifying a high value passes high frequencies.
Table 8–4. PMA Analog Options (Part 2 of 2)
Name Value Description
Figure 8–2. Top-Level PMA Signals
Note to Figure8–2:
(1) <n> is the number of channels or the number of PLLs. <d> is the deserialization factor.
tx_parallel_data<n>[<d>-1:0]
tx_parallel_clk[<n>-1:0]
rx_parallel_data<n>[<d>-1:0]
tx_ready[<n>-1:0]
rx_ready[<n>-1:0]
phy_mgmt_clk
phy_mgmt_reset
phy_mgmt_address[8:0]
phy_mgmt_writedata[31:0]
phy_mgmt_readdata[31:0]
phy_mgmt_write
phy_mgmt_read
phy_mgmt_waitrequest
pll_ref_clk
Low Latency PHY IP Core Top-Level Signals
tx_serial_data<n>
rx_serial_data<n>
rx_clkout[<n>-1:0]
rx_is_lockedtodata<n>[<n>-1:0]
rx_is_lockedtoref[<n>-1:0]
pll_locked[<n>-1:0]
tx_coreclkin[<n>-1:0]
rx_coreclkin[<n>-1>:0]
tx_bitslip
Avalon-ST Tx and Rx
to and from MAC
Avalon-MM PHY
Management
Interface
Optiona
l
Status
Stratix IV
Only
Serial
Data