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User Guide

Altera Transceiver PHY IP Core

Document last updated for Altera Complete Design Suite version:

Document publication date:

12.1

November 2012

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Altera Transceiver PHY IP Core User Guide

Summary of content (484 pages)

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Altera Transceiver PHY IP Core User Guide Altera Transceiver PHY IP Core User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com UG-01080-1.8 Document last updated for Altera Complete Design Suite version: Document publication date: 12.
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© 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.
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Contents Chapter 1. Introduction PCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3 PMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3 Avalon-MM PHY Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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iv ContentsContents Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–8 Link Training (LT), Clause 72 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–8 Auto Negotiation (AN), Clause 73 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9 Interfaces . . . . . . . . . .
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ContentsContents v Chapter 6. XAUI PHY IP Core Release Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2 Device Family Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2 Performance and Resource Utilization for Stratix IV Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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ContentsContents vi Serial Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–12 Register Interface and Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–12 Link Equalization for Gen3 Data Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–17 Phase 0 . . . . . . . . . . . . . .
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ContentsContents vii Chapter 11. Deterministic Latency PHY IP Core Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–2 Achieving Deterministic Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–3 Delay Estimation Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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viii ContentsContents Common Interface Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–32 Standard PCS Interface Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–35 10G PCS Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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ContentsContents ix Interlaken Frame Synchronizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14–24 Interlaken CRC32 Generator and Checker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14–26 10GBASE-R BER Checker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14–26 64b/66b Encoder and Decoder . . . . . . . . . . . . . . . .
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x ContentsContents Offset Cancellation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–12 Duty Cycle Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–12 Auxiliary Transmit (ATX) PLL Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–12 PMA Analog Control Registers . . . . . . .
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ContentsContents xi Chapter 19. Migrating from Stratix IV to Stratix V Devices Differences in Dynamic Reconfiguration for Stratix IV and Stratix V Transceivers . . . . . . . . . . . . . . . 19–2 Differences Between XAUI PHY Parameters for Stratix IV and Stratix V Devices . . . . . . . . . . . . . . . . 19–3 Differences Between XAUI PHY Ports in Stratix IV and Stratix V Devices . . . . . . . . . . . . . . . . . . . . . .
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xii Altera Transceiver PHY IP Core User Guide ContentsContents November 2012 Altera Corporation
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1. Introduction The Altera® Transceiver PHY IP Core User Guide describes the following types of transceiver PHYs: ■ Protocol-Specific Transceiver PHYs—These PHYs automatically configure settings for the physical coding sublayer (PCS) to meet the requirements of a specific protocol, leaving a small number of parameters in the physical media attachment (PMA) module for you to configure.
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1–2 Chapter 1: Introduction ■ Native Transceiver PHYs—These PHYs provide complete access to the low-level PCS and PMA hardware, allowing you to customize the transceiver settings to meet your requirements. Depending on protocol mode selected, built-in rules validate the options you select. Figure 1–2 illustrates the Native PHY IP Core for the Stratix V device. Figure 1–2.
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Chapter 1: Introduction 1–3 For detailed information about these IP cores, refer to the following chapters: ■ ■ Stratix V Transceiver Native PHY IP Core ■ Arria V Transceiver Native PHY IP Core ■ Arria V GZ Transceiver Native PHY IP Core ■ Cyclone V Transceiver Native PHY IP Core Additional PHYs—These PHYs provide more flexible settings than the protocol-specific transceiver PHYs.
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1–4 Chapter 1: Introduction Transceiver Reconfiguration Controller Altera Transceiver Reconfiguration Controller dynamically reconfigures analog settings in Arria V, Cyclone V, and Stratix V devices. Reconfiguration allows you to compensate for variations due to process, voltage, and temperature (PVT) in 28-nm devices. It is required for Arria V, Cyclone V, and Stratix V devices that include transceivers.
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Chapter 1: Introduction Running a Simulation Testbench 1–5 Running a Simulation Testbench When you generate your transceiver PHY IP core, the Quartus® II software generates the HDL files that define your parameterized IP core. In addition, the Quartus II software generates an example Tcl script to compile and simulate your design in ModelSim. Figure 1–3 illustrates the directory structure for the generated files. Figure 1–3. Directory Structure for Generated Files .v or .
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1–6 Chapter 1: Introduction Unsupported Features The Verilog and VHDL transceiver PHY IP cores have been tested with the following simulators: ■ ModelSim SE ■ Synopsys VCS MX ■ Cadence NCSim If you select VHDL for your transceiver PHY, only the wrapper generated by the Quartus II software is in VHDL. All the underlying files are written in Verilog or System Verilog.
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2. Getting Started This chapter provides a general overview of the Altera IP core design flow to help you quickly get started with any Altera IP core. The Altera IP Library is installed as part of the Quartus II installation process. You can select and parameterize any Altera IP core from the library. Altera provides an integrated parameter editor that allows you to customize IP cores to support a wide variety of applications.
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2–2 Chapter 2: Getting Started MegaWizard Plug-In Manager Flow ■ MegaWizard™ Plug-In Manager Flow Figure 2–2.
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Chapter 2: Getting Started MegaWizard Plug-In Manager Flow 2–3 2. In the Quartus II software, launch the MegaWizard Plug-in Manager from the Tools menu, and follow the prompts in the MegaWizard Plug-In Manager interface to create or edit a custom IP core variation. 3. To select a specific Altera IP core, click the IP core in the Installed Plug-Ins list in the MegaWizard Plug-In Manager. 4. Specify the parameters on the Parameter Settings pages.
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2–4 Chapter 2: Getting Started MegaWizard Plug-In Manager Flow 1 The Finish button may be unavailable until all parameterization errors listed in the messages window are corrected. 8. Click Yes if you are prompted to add the Quartus II IP File (.qip) to the current Quartus II project. You can also turn on Automatically add Quartus II IP Files to all projects. You can now integrate your custom IP core instance in your design, simulate, and compile.
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3. 10GBASE-R PHY IP Core The Altera 10GBASE-R PHY IP Core implements the functionality described in IEEE 802.3 Clause 49. It delivers serialized data to an optical module that drives optical fiber at a line rate of 10.3125 gigabits per second (Gbps). In a multi-channel implementation of 10GBASE-R, each channel of the 10GBASE-R PHY IP Core operates independently. Figure 3–1 shows the 10GBASE-R PHY IP Core available for Stratix V devices.
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3–2 Chapter 3: 10GBASE-R PHY IP Core 1 This configuration does not require that all four channels in a quad run the 10GBASE-R protocol. Figure 3–2. Complete 10GBASE-R PHY Design in Stratix IV GT Device 10GBASE-R PHY - Stratix IV Device SDR XGMII 72 bits @ 156.25 Mbps To MAC PCS 10GBASE-R (64b/66b) S Alt_PMA 10GBASE-R 10.3 Gbps To HSSI Pins S 10.3125 Gbps serial SDR XGMII 72 bits @ 156.25 Mbps To MAC PCS 10GBASE-R (64b/66b) S Alt_PMA 10GBASE-R 10.3 Gbps To HSSI Pins S 10.
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Chapter 3: 10GBASE-R PHY IP Core 3–3 Figure 3–3 illustrates the 10GBASE-R PHY for Arria V GT devices. Figure 3–3.
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3–4 Chapter 3: 10GBASE-R PHY IP Core Figure 3–5 illustrates the 10GBASE-R PHY for Stratix V devices. Figure 3–5.
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Chapter 3: 10GBASE-R PHY IP Core Release Information 3–5 Release Information Table 3–3 provides information about this release of the 10GBASE-R PHY IP Core. Table 3–3. 10GBASE-R Release Information Item Description Version 12.1 Release Date Ordering Codes November 2012 (1) IP-10GBASERPCS (primary) IPR-10GBASERPCS (renewal) Product ID 00D7 Vendor ID 6AF7 Note to Table 3–3: (1) No ordering codes or license files are required for Stratix V devices.
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3–6 Chapter 3: 10GBASE-R PHY IP Core Performance and Resource Utilization for Stratix IV Devices Performance and Resource Utilization for Stratix IV Devices .Table 3–5 shows the typical expected device resource utilization for duplex channels using the current version of the Quartus II software targeting a Stratix IV GT device. The numbers of combinational ALUTs, logic registers, and memory bits are rounded to the nearest 100. Table 3–5.
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Chapter 3: 10GBASE-R PHY IP Core Parameterizing the 10GBASE-R PHY 3–7 Parameterizing the 10GBASE-R PHY The 10GBASE-R PHY IP Core is available for the Arria V, Arria V GZ, Stratix IV, or Stratix V device families. Complete the following steps to configure the 10GBASE-R PHY IP Core in the MegaWizard Plug-In Manager: 1. For Which device family will you be using?, select Arria V, Arria V GZ, Stratix IV, or Stratix V from the list. 2. Click Installed Plug-Ins > Interfaces > Ethernet> 10GBASE-R PHY v12.1. 3.
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3–8 Chapter 3: 10GBASE-R PHY IP Core General Option Parameters Table 3–8. General Options (Part 2 of 2) Name Reference Clock Frequency Value Description 322.265625 MHz 644.53125 MHz Arria V and Stratix V devices support both frequencies. Stratix IV GT devices only support 644.53125 MHz.
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Chapter 3: 10GBASE-R PHY IP Core Analog Parameters 3–9 Analog Parameters Click on the appropriate link to specify the analog options for your device: ■ Analog Settings for Arria V Devices ■ Analog Settings for Arria V GZ Devices ■ Analog Parameters for Stratix IV Devices ■ Analog Settings for Stratix V Devices Analog Parameters for Stratix IV Devices For Stratix IV devices, you specify analog options on the Analog Options tab. Table 3–9 describes these options. Table 3–9.
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3–10 Chapter 3: 10GBASE-R PHY IP Core Interfaces Interfaces Figure 3–6 illustrates the top-level signals of the 10BASE-R PHY. In Figure 3–6, is the channel number. Figure 3–6.
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Chapter 3: 10GBASE-R PHY IP Core Data Interfaces 3–11 Data Interfaces Table 3–10 describes the signals in the SDR XGMII TX and RX interface. The TX signals are driven from the MAC to the PCS. The RX signals are driven from the PCS to the MAC. Table 3–10. SDR XGMII TX Inputs (Part 1 of 2) Signal Name Direction Description XGMII TX Interface Contains 8 lanes of data and control for XGMII. Each lane consists of 8 bits of data and 1 bit of control.
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3–12 Chapter 3: 10GBASE-R PHY IP Core Data Interfaces Table 3–10. SDR XGMII TX Inputs (Part 2 of 2) Signal Name Direction Description Output When asserted, indicates that the PCS is sending data to the MAC. Because the readyLatency on this Avalon-ST interface is 0, the MAC must be ready to receive data whenever this signal is asserted. After rx_ready is asserted indicating the exit from the reset state, the MAC should store xgmii_rx_dc_[71:0] in each cycle where rx_data_ready is asserted.
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Chapter 3: 10GBASE-R PHY IP Core Status, 1588, and PLL Reference Clock Interfaces 3–13 Table 3–12 provides the mapping from the XGMII RX interface to the XGMII SDR interface. Table 3–12.
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3–14 Chapter 3: 10GBASE-R PHY IP Core Clocks for Arria V GT Devices Clocks for Arria V GT Devices Figure 3–7 illustrates the clock generation and distribution for Arria V GT devices. Figure 3–7. Arria V GT Clock Generation and Distribution 10GBASE-R Transceiver Channel - Arria V GT TX 64 64 TX PCS (soft) TX PMA (hard) 161.1328 MHz xgmii_tx_clk 156.25 MHz 80 10.3125 Gbps pll_ref_clk 644.53125 MHz TX PLL RX 64 64 RX PCS (soft) rx_coreclkin 161.1328 MHz RX PMA (hard) 80 10.
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Chapter 3: 10GBASE-R PHY IP Core Clocks for Arria V GZ Devices 3–15 Clocks for Arria V GZ Devices Figure 3–8 illustrates the clock generation and distribution for Arria V GZ devices Figure 3–8. Arria V GZ Clock Generation and Distribution 10GBASE-R Hard IP Transceiver Channel - Arria V GZ TX 64-bit data, 8-bit control xgmii_tx_clk 10.3125 Gbps serial 40 TX PCS TX PMA 257.8125 MHz RX RX PCS 156.25 MHz rx_coreclkin 10.
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3–16 Chapter 3: 10GBASE-R PHY IP Core Clocks for Stratix IV Devices The PCS runs at 257.8125 MHz using the pma_rx_clock provided by the PMA. You must provide the PMA an input reference clock running at 644.53725 MHz to generate the 257.8125 MHz clock. Figure 3–9 illustrates the clock generation and distribution for Stratix IV devices. Figure 3–9.
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Chapter 3: 10GBASE-R PHY IP Core Clocks for Stratix V Devices 3–17 Clocks for Stratix V Devices Figure 3–10 illustrates the clock generation and distribution for Stratix V devices. Figure 3–10. Stratix V Clock Generation and Distribution 10GBASE-R Hard IP Transceiver Channel - Stratix V TX 64-bit data, 8-bit control xgmii_tx_clk 10.3125 Gbps serial 40 TX PCS TX PMA TX PLL 257.8125 MHz RX xgmii_rx_clk RX PCS 156.25 MHz rx_coreclkin 10.
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3–18 Chapter 3: 10GBASE-R PHY IP Core Register Interface and Register Descriptions Table 3–14 describes the signals that comprise the Avalon-MM PHY Management interface. Table 3–14. Avalon-MM PHY Management Interface Signal Name Direction Description The clock signal that controls the Avalon-MM PHY management, interface. For Stratix IV devices, the frequency range is 37.5–50 MHz.
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Chapter 3: 10GBASE-R PHY IP Core Register Interface and Register Descriptions 3–19 Table 3–15. 10GBASE-R Register Descriptions (Part 2 of 3) Word Addr Bit R/W Name Description Reset Control Registers–Automatic Reset Controller 0x041 0x042 0x044 [31:0] reset_ch_bitmask Reset controller channel bitmask for digital resets. The default value is all 1 s. Channel can be reset when bit = 1. Channel cannot be reset when bit=0.
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3–20 Chapter 3: 10GBASE-R PHY IP Core Register Interface and Register Descriptions Table 3–15. 10GBASE-R Register Descriptions (Part 3 of 3) Word Addr Bit R/W Name Description 10GBASE-R PCS 0x080 [31:0] WO INDIRECT_ADDR [2] RW RCLR_ERRBLK_CNT [3] RW RCLR_BER_COUNT [0] R PCS_STATUS When set to 1, clears the error block count register. 0x081 [1] R Provides for indirect addressing of all PCS control and status registers.
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Chapter 3: 10GBASE-R PHY IP Core Dynamic Reconfiguration for Stratix IV Devices 3–21 Dynamic Reconfiguration for Stratix IV Devices Table 3–16 describes the additional top-level signals 10GBASE-R PHY IP Core when the configuration uses external modules for PMA control and reconfiguration. You enable this configuration by turning on Use external PMA control and reconfig available for Stratix IV GT devices. Table 3–16.
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3–22 Chapter 3: 10GBASE-R PHY IP Core TimeQuest Timing Constraints Table 3–17 describes the signals in the reconfiguration interface. This interface uses the Avalon-MM PHY Management interface clock. Table 3–17. Reconfiguration Interface Signal Name reconfig_to_xcvr [(70-1):0] reconfig_from_xcvr [(46-1):0] Direction Description Input Reconfiguration signals from the Transceiver Reconfiguration Controller. grows linearly with the number of reconfiguration interfaces.
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Chapter 3: 10GBASE-R PHY IP Core TimeQuest Timing Constraints 3–23 #************************************************************** Example 3–3.
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3–24 Chapter 3: 10GBASE-R PHY IP Core TimeQuest Timing Constraints Synopsys Design Constraints for Clocks (Continued) # Set Clock Groups #************************************************************** set_clock_groups -exclusive -group phy_mgmt_clk -group xgmii_tx_clk -group [get_clocks {*siv_alt_pma|pma_ch*.pma_direct|transmit_pcs*|clkout}] -group [get_clocks {*siv_alt_pma|pma_ch*.
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Chapter 3: 10GBASE-R PHY IP Core Simulation Files and Example Testbench 3–25 Simulation Files and Example Testbench Refer to Running a Simulation Testbench for a description of the directories and files that the Quartus II software creates automatically when you generate your 10GBASE-R PHY IP Core. f Refer to the Altera wiki for an example testbench that you can use as a starting point in creating your own verification environment.
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3–26 Altera Transceiver PHY IP Core User Guide Chapter 3: 10GBASE-R PHY IP Core Simulation Files and Example Testbench November 2012 Altera Corporation
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4. Backplane Ethernet 10GBASE-KR PHY IP Core The Backplane Ethernet 10GBASE-KR PHY MegaCore® function is available for Stratix® V and Arria V GZ devices. This transceiver PHY allows you to instantiate both the hard Standard PCS and the higher performance hard 10G PCS and hard PMA for a single Backplane Ethernet channel. It implements the functionality described in the IEEE Std 802.3ap-2007 Standard.
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Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core Release Information 1 4–2 Forward error correction (FEC) which is an optional feature of IEEE Std 802.3ap-2007 is not available for this release. Release Information Table 4–1 provides information about this release of the 10GBASE-KR PHY IP Core. Table 4–1. 10GBASE-KR PHY Release Information Item Description Version 12.
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Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core Performance and Resource Utilization 4–3 Performance and Resource Utilization Table 4–3 shows the typical expected device resource utilization for selected configurations using the current version of the Quartus II software targeting a Stratix V GT (5SGTMC7K2F40C2) device. The numbers of ALMs and logic registers in Table 4–3 are rounded up to the nearest 100.
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Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core Link Training Parameters and Auto-Negotiation Parameters 4–4 4. Refer to the following topics to learn more about the parameters: a. Link Training Parameters and Auto-Negotiation Parameters b. Parameters and Speed Negotiation Parameters c. Analog Parameters 5. Click Finish to generate your customized 10GBASE-KR PHY IP Core.
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Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core Parameters and Speed Negotiation Parameters 4–5 Table 4–4. Link Training Name Range Description PREMAINVAL 0-63 Specifies the Preset VOD Value. Set by the Preset command as defined in Clause 72.6.10.2.3.1 of the link training protocol. This is the value from which the algorithm starts. The default value is 60. PREPOSTVAL 0-31 Specifies the preset Post-tap value. The default value is 0. PREPREVAL 0-15 Specifies the preset Pre-tap Value.
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Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core Parameters and Speed Negotiation Parameters 4–6 Table 4–7 describes the parameters to specify 1Gb Ethernet parameters. Table 4–7. 1 Gb Ethernet Parameter Name Options Description Enable 1Gb Ethernet protocol On/Off When you turn this option On, the core includes the GMII interface and related logic. Enable SGMII bridge logic. On/Off When you turn this option On, the core includes the SGMII clock and rate adaptation logic for the PCS.
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Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core Analog Parameters 4–7 Table 4–8. Speed Detection (Part 2 of 2) Parameter Name Link fail inhibit t time for 10Gb Ethernet Link fail inhibit t time for 1Gb Ethernet Options Description 504 ms Specifies the time before link_status is set to FAIL or OK. A link fails if the link_fail_inhibit_time has expired before link_status is set to OK. For 10GBASE-KR the legal range is 500–510 ms.
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Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core Functional Description 4–8 Functional Description Figure 4–2 shows the 10GBASE-KR PHY IP Core and the supporting modules required for integration into your system. The following sections provide an overview of these modules. Figure 4–2.
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Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core Functional Description 4–9 Auto Negotiation (AN), Clause 73 The Auto Negotiation module in the 10GBASE-KR PHY IP implements Clause 73 of the Ethernet standard. This module currently supports auto negotiation between 1GbE and 10GBASE-R data rates. Auto negotiation with XAUI is not supported. Auto negotiation is run upon power up or if the auto negotiation module is reset.
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Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core Interfaces 4–10 Interfaces Figure 4–3 shows the top-level signals of the Backplane Ethernet 10GBASE-KR IP Core. Figure 4–3.
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Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core Clock and Reset Interfaces 1 4–11 The block diagram shown in the GUI labels the external pins with the interface type and places the interface name inside the box. The interface type and name are used in the _hw.tcl file. If you turn on Show signals, the block diagram displays all top-level signal names. f For more information about _hw.tcl files, refer to refer to the Component Interface Tcl Reference chapter in volume 1 of the Quartus II Handbook.
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Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core Data Interfaces 4–12 Table 4–9 describes the clock and reset signals. The frequencies of the XGMII clocks increases to 257.8125 MHz when you enable 1588. Table 4–9. Clock and Reset Signals Signal Name Direction Description rx_recovered_clk Output The RX clock which is recovered from the received data. You can use this clock as a reference to lock an external clock source. Its frequency is 125 or 156.25 MHz.
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Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core Data Interfaces 4–13 Table 4–10. XGMII and GMII Signals (Part 2 of 2) Signal Name xgmii_rx_dc[71:0] xgmii_rx_clk Direction Description Output RX XGMII data and control for 8 lanes. Each lane consists of 8 bits of data and 1 bit of control. Input Clock for SDR XGMII RX interface to the MAC.The frequency is 156.25 MHz. When you enable 1588 the frequency is 257.8125 MHz. 1G/10GbE GMII Data Interface gmii_tx_d[7:0] Input TX data for 1G mode.
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Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core Data Interfaces 4–14 Table 4–11.
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Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core Control and Status Interfaces 4–15 Control and Status Interfaces Table 4–13 describes the control and status interface signals. Table 4–14. Control and Status Signals (Part 1 of 2) Signal Name Direction Description rx_block_lock Output Asserted to indicate that the block synchronizer has established synchronization. rx_hi_ber Output Asserted by the BER monitor block to indicate a Sync Header high bit error rate greater than 10-4.
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Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core PHY Link Training 4–16 Table 4–14. Control and Status Signals (Part 2 of 2) Signal Name Direction Description rx_latency_adj_10g[11:0] Output When you enable 1588, this signal outputs the real time latency in XGMII clock cycles (156.25 MHz) for the RX PCS and PMA datapath for 10G mode. tx_latency_adj_10g[11:0] Output When you enable 1588, this signal outputs real time latency in XGMII clock cycles (156.
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Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core Daisy-Chain Mode 4–17 Daisy-Chain Mode Figure 4–6 illustrates equalization in daisy-chain mode. In daisy-chain mode the devices are connected over a backplane in a daisy-chain topology instead of in a spoke and hub or switch topology. Figure 4–6.
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Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core Embedded Processor Mode Interface 4–18 Table 4–15 describes the signals that permit a daisy-chain mode for Link Training. Table 4–15. Daisy Chain Mode Signal Name Role Description dmi_mode_en input When asserted, enable Daisy Chain mode. dmi_frame_lock input When asserted, the daisy chain state machine has locked to the training frames. dmi_rmt_rx_ready Input Corresponds to bit 15 of Status report field. When asserted, the remote receiver.
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Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core Register Interface and Register Descriptions 4–19 Table 4–16. Embedded Processor Link Training Signals (Part 2 of 2) Signal Name Role Description upi_pre Input When asserted, sends the preset command. upi_init Input When asserted, sends the initialize command. upi_st_bert Input When asserted, starts the BER timer. upi_train_err Input When asserted, indicates a training error.
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Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core Register Interface and Register Descriptions 4–20 Table 4–18 specifies the control and status registers that you can access over the Avalon-MM PHY management interface. A single address space provides access to all registers. 1 Unless otherwise indicated, the default value of all registers is 0. 1 Writing to reserved or undefined register addresses may have undefined side effects. Table 4–18.
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Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core Register Interface and Register Descriptions 4–21 Table 4–18. 10GBASE-KR Register Definitions (Part 2 of 12) Word Address Bit R/W Name Description When set to 1, enables Auto-Negotiation function. The default value is 1. 0 1 RW RW AN enable AN base pages ctrl For additional information, refer to bit 7.0.12 in Clause 73.8 Management Register Requirements, of IEEE 802.3ap-2007. When set to 1, the user base pages are enabled.
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Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core Register Interface and Register Descriptions 4–22 Table 4–18. 10GBASE-KR Register Definitions (Part 3 of 12) Word Address Bit 1 R/W RO Name AN page received Description When set to 1, a page has been received. When 0, a page has not been received. The current value clears when the register is read. For more information, refer to bit 7.1.6 in Clause 73.8 of IEEE 802.3ap-2007.
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Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core Register Interface and Register Descriptions 4–23 Table 4–18. 10GBASE-KR Register Definitions (Part 4 of 12) Word Address Bit R/W Name 9 RO Seq AN Failure Description When set to 1, a sequencer Auto-Negotiation failure has been detected. When set to 0, a Auto-Negotiation failure has not been detected. Provides a one-hot encoding of an_receive_idle = true and link status for the supported link as described in Clause 73.10.1.
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Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core Register Interface and Register Descriptions 4–24 Table 4–18. 10GBASE-KR Register Definitions (Part 5 of 12) Word Address Bit R/W Name Description The Auto-Negotiation TX state machine uses these bits if the Auto-Negotiation next pages ctrl bit is set. The following bits are defined: 0xC5 15:0 RW User Next page low ■ [15]: next page bit ■ [14]: ACK controlled by the state machine ■ [13]: Message Page (MP) bit ■ [12]: ACK2 bit ■ [11]: .
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Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core Register Interface and Register Descriptions 4–25 Table 4–18. 10GBASE-KR Register Definitions (Part 6 of 12) Word Address Bit 0xCA 31:0 R/W RO Name LP Next page high Description The AN RX state machine receives these bits from the link partner. Bits [31:0] correspond to page bits [47:16] Received technology ability field bits of Clause 73 Auto-Negotiation. The 10GBASE-KR PHY supports A2.
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Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core Register Interface and Register Descriptions 4–26 Table 4–18. 10GBASE-KR Register Definitions (Part 7 of 12) Word Address Bit R/W Name Description 11:8 RW prpo_step_cnt[3:0] Specifies the number of equalization steps for each preand post- tap update. From 16-31 steps are possible. The default value is 4’b0001. 13:12 RW equal_cnt[1:0] Adds hysteresis to the error count to avoid local minimums. The default value is 2’b01.
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Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core Register Interface and Register Descriptions 4–27 Table 4–18. 10GBASE-KR Register Definitions (Part 8 of 12) Word Address Bit 2 R/W RO Name Link Training Start-up protocol status Description When set to 1, the start-up protocol is in progress. When set to 0, start-up protocol has completed. For more information, refer to the state training as defined in Clause 72.6.10.3.1 and bit 151.2 of IEEE 802.3ap-2007.
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4–28 Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core Register Interface and Register Descriptions Table 4–18. 10GBASE-KR Register Definitions (Part 9 of 12) Word Address Bit R/W Name Description Reflects the contents of the first 16-bit word of the training frame sent from the local device control channel. Normally, the bits in this register are read-only; however, when you override training by setting the Ovride Coef enable control bit, these bits become writeable.
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Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core Register Interface and Register Descriptions 4–29 Table 4–18. 10GBASE-KR Register Definitions (Part 10 of 12) Word Address Bit 14 R/W RO Name Link Training ready – LD Receiver ready Description When set to 1, the local device receiver has determined that training is complete and is prepared to receive data. When set to 0, the local device receiver is requesting that training continue. Values for the receiver ready bit are defined in Clause 72.6.
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4–30 Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core Register Interface and Register Descriptions Table 4–18.
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Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core 10GBASE-KR PHY PMA and PCS Registers 4–31 Table 4–18. 10GBASE-KR Register Definitions (Part 12 of 12) Word Address Bit R/W Name Description 13:8 RW LT VODMin ovrd Override value for the VODMINRULE parameter. When set to 1, this value substitutes for the VMINRULE to allow channel-by-channel override of the device settings. This override only effects the local device TX output for this channel.
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4–32 Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core 10GBASE-KR PHY 1GbE Registers Table 4–19. PMA Registers (Part 2 of 2) Bit Access Name Description 0x66 [31:0] RO pma_rx_is_lockedtodata When asserted, indicates that the RX CDR PLL is locked to the RX data, and that the RX CDR has changed from LTR to LTD mode. 0x67 [31:0] RO pma_rx_is_lockedtoref When asserted, indicates that the RX CDR PLL is locked to the reference clock.
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Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core Dynamic Reconfiguration from 1G to 10GbE 4–33 Table 4–21. 1G/10GbE PMA Registers (Part 2 of 2) address Bit R/W Name Description 0xA8 3 RW rx_bytereversal_enable When set, enables byte reversal on the RX interface. The RX data is input to the byte deserializer. 0xA8 4 RW force_electrical_idle When set to 1, forces the TX outputs to electrical idle.
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4–34 Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core Dynamic Reconfiguration from 1G to 10GbE Figure 4–7. Block Diagram for Reconfiguration Example 1G/10Gb Ethernet PHY MegaCore Function 1G/10Gb Ethernet PHY MegaCore Function 1G/10Gb Ethernet PHY MegaCore Function Native PHY Hard IP 1G/10Gb Ethernet MAC 1G/10Gb Ethernet MAC 1G/10Gb Ethernet MAC 10 Gb Ethernet Hard PCS RX XGMII Data TX GMII Data @ 125 MHz RX GMII Data Shared Across Multiple Channels 257.8 MHz TX XGMII Data @156.
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Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core Creating a 10GBASE-KR Design 4–35 State Machine Requirements The state machine shown in Figure 4–7 should implement the following logic. You can modify this logic based on your system requirements: 1. Wait for reconfig_busy from the Transceiver Reconfiguration Controller to be deasserted and the tx_ready and rx_ready signals from the Transceiver PHY Reset Controller to be asserted.
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4–36 Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core Editing a MIF File 8. Generate a fractional PLL to create the 156.25 MHz XGMII clock from the 10G reference clock. 9. Instantiate the PHY in your design to determine the required number of channels. 10. To complete the system, connect all the blocks. Editing a MIF File The MIF format contains all bit settings for the transceiver PMA and PCS.
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Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core Design Examples 4–37 Design Examples Altera has two design examples to assist you in integrating this PHY IP into your design. ■ A MAC and PHY design example. This design example instantiates the 1G/10GbE PHY IP along with the 1G/10G Ethernet MAC and supporting logic. It is part of the Quartus II 12.1 installation and is located in the /ip subdirectory.
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4–38 Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core Acronyms Table 4–22. Dynamic Reconfiguration Signals (Part 2 of 2) Signal Name Direction Description Specifies the PCS mode for reconfig using 1-hot encoding.
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Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core Acronyms 4–39 Table 4–23. Common Ethernet Acronyms (Part 2 of 2) Acronym Definition WAN Wide Area Network. XAUI 10 Gigabit Attachment Unit Interface.
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4–40 Altera Transceiver PHY IP Core User Guide Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core Acronyms November 2012 Altera Corporation
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5. 1G/10 Gbps Ethernet PHY IP Core The 1G/10 Gbps Ethernet PHY MegaCore® (1G/10GbE) function allows you to instantiate both the Standard PCS and the higher performance 10G PCS and a PMA. The Standard PCS implements the 1 GbE protocol as defined in Clause 36 of IEEE 802.3 2005 standard and also supports auto-negotiation as defined in Clause 37 of the IEEE 802.3 2005 standard. The 10G PCS implements the 10 Gb Ethernet protocol as defined in IEEE 802.3 2005 standard.
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Chapter 5: 1G/10 Gbps Ethernet PHY IP Core 1G/10GbE Release Information 5–2 An Avalon® Memory-Mapped (Avalon-MM) slave interface provides access to the 1G/10GbE PHY IP Core registers. These registers control many of the functions of the other blocks. Refer to Register Interface and Register Descriptions for more information about the available registers. Many of these bits are defined in Clause 45 of IEEE Std 802.3ap-2007.
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Chapter 5: 1G/10 Gbps Ethernet PHY IP Core Parameterizing the 1G/10GbE PHY 5–3 f For information about Quartus II resource utilization reporting, refer to Fitter Resources Reports in the Quartus II Help. Table 5–3.
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Chapter 5: 1G/10 Gbps Ethernet PHY IP Core Parameterizing the 1G/10GbE PHY 5–4 10GBASE-R Parameters Table 5–4 describes the parameters to specify 10GBASE-R PCS. Table 5–4. 10GBASE-R Parameters Parameter Name Enable IEEE 1588 Precision Time Protocol Reference clock frequency Options Description On/Off When you turn this option On, the core includes logic to implement the IEEE 1588 Precision Time Protocol. 644.53125MHz Specifies the clock frequency for the 1GBASE-KR PHY IP Core. The 322.
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Chapter 5: 1G/10 Gbps Ethernet PHY IP Core Analog Parameters 5–5 Speed Detection Table 5–6 describes the parameters to specify speed detection parameters. By selecting the Enable automatic speed detection option in the Megawizard, the PHY IP implement Parallel Detect as described in the Ethernet specification. Selecting this option causes the PHY to start in 10G mode and wait for a link_good signal from the PCS.
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Chapter 5: 1G/10 Gbps Ethernet PHY IP Core Interfaces 5–6 Interfaces Figure 5–2 shows the top-level signals of the 1G/10GbE IP Core. Some of the signals shown in are Figure 5–2 unused and will be removed in a future release. The descriptions of these identifies them as not functional. Figure 5–2.
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Chapter 5: 1G/10 Gbps Ethernet PHY IP Core Clock and Reset Interfaces 5–7 Phy_mgmt_clk_reset is the system-level reset signal. Phy_mgmt_clk_reset is also an input to the Transceiver PHY Reset Controller IP Core which is a separately instantiated module not included in the 1G/10GbE and 10GBASE-KR variants. The Transceiver PHY Reset Controller IP Core resets the TX PLL and RX analog circuits and the TX and RX digital circuits. When complete, the Reset Controller asserts the tx_ready and rx_ready signals.
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Chapter 5: 1G/10 Gbps Ethernet PHY IP Core Data Interfaces 5–8 Table 5–7. Clock and Reset Signals (Part 2 of 2) Signal Name Direction Description rx_clkout_1g Output GMII RX clock for the 1G RX parallel data source interface. The frequency is 125 MHz. rx_clkout_10g Output XGMII RX clock for the 10G RX parallel data source interface. The frequency is 257.8125 MHz. rx_coreclkin_1g Input Optional clock to drive the read side of the RX phase compensation FIFO in the Standard PCS.
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Chapter 5: 1G/10 Gbps Ethernet PHY IP Core Data Interfaces 5–9 Table 5–8. XGMII and GMII Signals (Part 2 of 2) Signal Name Direction Description gmii_tx_err Input When asserted, indicates an error. May be asserted at any time during a frame transfer to indicate an error in that frame gmii_rx_err Output When asserted, indicates an error. May be asserted at any time during a frame transfer to indicate an error in that frame gmii_rx_dv Output When asserted, indicates the start of a new frame.
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Chapter 5: 1G/10 Gbps Ethernet PHY IP Core Control and Status Interfaces 5–10 Table 5–11 describes the serial data interface signals. Table 5–10.
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Chapter 5: 1G/10 Gbps Ethernet PHY IP Core Register Interface and Register Descriptions 5–11 Table 5–12. Control and Status Signals (Part 2 of 2) Signal Name Direction Description Input This clock is used for calculating the latency of the soft 1G PCS block. This clock is only required for when you enable 1588 in 1G mode. rx_sync_status Output When asserted, indicates the word aligner has aligned to in incoming word alignment pattern.
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Chapter 5: 1G/10 Gbps Ethernet PHY IP Core Register Interface and Register Descriptions 5–12 Table 5–13. Avalon-MM PHY Management Signals Signal Name Direction Description mgmt_addr[7:0] Input 9-bit Avalon-MM address. Refer to for the address fields. mgmt_writedata[31:0] Input Input data. mgmt_readdata[31:0] Output Output data. mgmt_write Input Write signal. Asserted high. mgmt_read Input Read signal. Asserted high.
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Chapter 5: 1G/10 Gbps Ethernet PHY IP Core Register Interface and Register Descriptions 5–13 Table 5–14. 1G/10GbE Register Definitions address Bit 0 R/W RW Name Description Reset SEQ When set to 1, resets the 1G/10GbE-KR sequencer. May also initiate PCS reconfiguration, Auto-Negotiation, or Link Training resets. This bit must be used in conjunction with SEQ Force Mode[2:0]. This reset self clears. 1 RW Disable AN Timer Auto-Negotiation disable timer.
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Chapter 5: 1G/10 Gbps Ethernet PHY IP Core Register Interface and Register Descriptions 5–14 Table 5–15. PMA Registers (Part 2 of 2) Bit Access 0x65 0 RW pma_rx_set_locktoref When set, programs the RX clock data recovery (CDR) PLL to lock to the reference clock. 0x66 0 RO pma_rx_is_lockedtodata When asserted, indicates that the RX CDR PLL is locked to the RX data, and that the RX CDR has changed from LTR to LTD mode.
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Chapter 5: 1G/10 Gbps Ethernet PHY IP Core Register Interface and Register Descriptions 5–15 GMII PCS Registers Table 5–17 describes the 1G/10GbE GMII PCS registers. Table 5–17. GMII PCS Registers (Part 1 of 2) address 0x90 0x91 Bit R/W Name Description 9 RW RESTART_AUTO_ NEGOTIATION Set this bit to 1 to restart the Clause 37 Auto-Negotiation sequence. For normal operation, set this bit to 0 which is the default value.
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Chapter 5: 1G/10 Gbps Ethernet PHY IP Core Register Interface and Register Descriptions 5–16 Table 5–17. GMII PCS Registers (Part 2 of 2) address Bit R/W Name Description 5 R FD Full-duplex mode enable for the link partner. A value of 1 should be set to indicates support for full duplex. 6 R HD Half-duplex mode enable for the link partner. A value of 1 indicates support for half duplex. This bit should always be 0 for the 10GBASE-KR PHY. Specifies pause support for link partner.
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Chapter 5: 1G/10 Gbps Ethernet PHY IP Core Dynamic Reconfiguration from 1G to 10GbE 5–17 Table 5–18. 1G/10GbE PMA Registers (Part 2 of 2) address Bit R/W 0xA8 4 RW 0xA9 0 0xA9 Name Description force_electrical_idle When set to 1, forces the TX outputs to electrical idle. R rx_syncstatus When set to 1, indicates that the word aligner is synchronized to incoming data. 1 R rx_patterndetect When set to 1, indicates the 1G word aligner has detected a comma.
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Chapter 5: 1G/10 Gbps Ethernet PHY IP Core Dynamic Reconfiguration from 1G to 10GbE 5–18 Figure 5–4. Block Diagram for Reconfiguration Example 1G/10Gb Ethernet PHY MegaCore Function 1G/10Gb Ethernet PHY MegaCore Function 1G/10Gb Ethernet PHY MegaCore Function Native PHY Hard IP 1G/10Gb Ethernet MAC 1G/10Gb Ethernet MAC 1G/10Gb Ethernet MAC 257.8 MHz TX XGMII Data @156.
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Chapter 5: 1G/10 Gbps Ethernet PHY IP Core Creating a 1G/10GbE Design 5–19 State Machine Requirements The state machine shown in Figure 5–4 should implement the following logic. You can modify this logic based on your system requirements: 1. Wait for reconfig_busy from the Transceiver Reconfiguration Controller to be deasserted and the tx_ready and rx_ready signals from the Transceiver PHY Reset Controller to be asserted.
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Chapter 5: 1G/10 Gbps Ethernet PHY IP Core Editing a MIF File 5–20 8. Generate a fractional PLL to create the 156.25 MHz XGMII clock from the 10G reference clock. 9. Instantiate the PHY in your design to determine the required number of channels. 10. To complete the system, connect all the blocks. Editing a MIF File The MIF format contains all bit settings for the transceiver PMA and PCS.
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Chapter 5: 1G/10 Gbps Ethernet PHY IP Core Design Examples 5–21 Example 5–1 illustrates the original and edited MIFs with changed text in red. The example shown is only the beginning lines of the MIF to modify. The complete original MIF is 168 lines. The complete edited MIF is 164 lines. Example 5–1.
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Chapter 5: 1G/10 Gbps Ethernet PHY IP Core Dynamic Reconfiguration 5–22 Dynamic Reconfiguration Table 5–19 describes the signals the dynamic reconfiguration interface. Table 5–19. Dynamic Reconfiguration Signals Signal Name reconfig_to_xcvr [(70-1):0] reconfig_from_xcvr [(46-1):0] rc_busy Direction Input Description Reconfiguration signals from the Reconfiguration Design Example. grows linearly with the number of reconfiguration interfaces.
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Chapter 5: 1G/10 Gbps Ethernet PHY IP Core Simulation 5–23 Simulation The 1G/10GbE PHY IP Core support ModelSim Verilog and ModelSim VHDL, VCS Verilog, and VCS VHDL simulation. Stratix V devices also support NCSIM Verilog and MCSIM VHDL simulation. The MegaWizard Plug-In Manager generates an IP functional simulation model when you press the Finish button. TimeQuest Timing Constraints To pass timing analysis, you must decouple the clocks in different time domains.
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5–24 Altera Transceiver PHY IP Core User Guide Chapter 5: 1G/10 Gbps Ethernet PHY IP Core Acronyms November 2012 Altera Corporation
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6. XAUI PHY IP Core The Altera XAUI PHY IP Core implements the IEEE 802.3 Clause 48 specification to extend the operational distance of the XGMII interface and reduce the number of interface signals. XAUI extends the physical separation possible between the 10 Gbps Ethernet MAC function and the Ethernet standard PHY component to one meter. The XAUI IP Core accepts 72-bit data (single data rate–SDR XGMII) from the application layer at either 156.25 Mbps or 312.5 Mbps.
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6–2 Chapter 6: XAUI PHY IP Core Release Information Release Information Table 6–1 provides information about this release of the XAUI PHY IP Core. Table 6–1. XAUI Release Information Item Description Version 12.
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Chapter 6: XAUI PHY IP Core Performance and Resource Utilization for Stratix IV Devices 6–3 Performance and Resource Utilization for Stratix IV Devices Table 6–3 shows the typical expected device resource utilization for different configurations using the current version of the Quartus II software targeting a Stratix IV GX (EP4SG230KF40C2ES) device. The numbers of combinational ALUTs, logic registers, and memory bits are rounded to the nearest 100. Table 6–3.
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6–4 Chapter 6: XAUI PHY IP Core General Parameters General Parameters Table 6–4 lists the settings available on General Options tab. Table 6–4. General Options (Part 1 of 2) Name Device family Value Description Arria II GX Arria V Arria V GZ Cyclone IV GX The target device family. Cyclone V, HardCopy IV Stratix IV Stratix V The physical starting channel number in the Altera device for channel 0 of this XAUI PHY.
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Chapter 6: XAUI PHY IP Core Analog Parameters 6–5 Table 6–4. General Options (Part 2 of 2) Name Base data rate Number of XAUI interfaces Value Description 1 × Lane rate 2 × Lane rate 4 × Lane rate The base data rate is the frequency of the clock input to the PLL. Select a base data rate that minimizes the number of PLLs required to generate all the clock s required for data transmission.
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6–6 Chapter 6: XAUI PHY IP Core Analog Parameters for Arria II GX, Cyclone IV GX, HardCopy IV and Stratix IV Devices Analog Parameters for Arria II GX, Cyclone IV GX, HardCopy IV and Stratix IV Devices Arria II GX, Cyclone IV GX, and Stratix IV devices, you specify analog options on the Analog Options tab. Table 6–5 describes these options. Table 6–5.
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Chapter 6: XAUI PHY IP Core Advanced Options Parameters 6–7 Advanced Options Parameters Table 6–6 describes the settings available on the Advanced Options tab. Table 6–6. Advanced Options Name Include control and status ports External PMA control and configuration Value Description On/Off If you turn this option on, the top-level IP core include the status signals and digital resets shown in XAUI Top-Level Signals—Soft PCS and PMA and XAUI Top-Level Signals–Hard IP PCS and PMA.
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6–8 Chapter 6: XAUI PHY IP Core Configurations Configurations Figure 6–2 illustrates one configuration of the XAUI IP Core. As this figure illustrates, if your variant includes a single instantiation of the XAUI IP Core, the transceiver reconfiguration control logic is included in the XAUI PHY IP Core. For Arria V, Cyclone V, and Stratix V devices the Transceiver Reconfiguration Controller must always be external.
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Chapter 6: XAUI PHY IP Core Ports 1 6–9 The block diagram shown in the GUI labels the external pins with the interface type and places the interface name inside the box. The interface type and name are used to define component interfaces in the _hw.tcl. If you turn on Show signals, the block diagram displays all top-level signal names. f For more information about _hw.tcl files refer to refer to the Component Interface Tcl Reference chapter in volume 1 of the Quartus II Handbook.
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6–10 Chapter 6: XAUI PHY IP Core Data Interfaces Figure 6–4 illustrates the top-level signals of the XAUI PHY IP Core for the soft IP implementation for both the single and DDR rates. Figure 6–4.
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Chapter 6: XAUI PHY IP Core Data Interfaces 6–11 For the DDR XAUI variant, the start of control character (0xFB) is aligned to either byte 0 or byte 5. Figure 6–6 illustrates byte 0 alignment. Figure 6–6.
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6–12 Chapter 6: XAUI PHY IP Core Data Interfaces SDR XGMII TX Interface Table 6–7 describes the signals in the SDR TX XGMII interface. Table 6–7. SDR TX XGMII Interface Signal Name Direction Description Contains 4 lanes of data and control for XGMII. Each lane consists of 16 bits of data and 2 bits of control.
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Chapter 6: XAUI PHY IP Core Clocks, Reset, and Powerdown Interfaces 6–13 Clocks, Reset, and Powerdown Interfaces Figure 6–8 illustrates the clock inputs and outputs for the XAUI IP Cores with hard PCS and PMA blocks. Figure 6–8. Clock Inputs and Outputs, Hard PCS phy_mgmt_clk XAUI Hard IP Core pll_ref_clk pll_inclk Hard PCS xgmii_tx_clk rx_cruclk PMA 4 tx_coreclk xgmii_rx_clk 4 coreclkout 4 x 3.
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6–14 Chapter 6: XAUI PHY IP Core PMA Channel Controller Interface PMA Channel Controller Interface Table 6–11 describes the signals in this interface. Table 6–11. PMA Channel Controller Signals Signal Name Direction Description cal_blk_powerdown Input Powers down the calibration block. A high-to-low transition on this signal restarts calibration. Only available in Arria II GX, HardCopy IV, and Stratix IV GX, and Stratix IV GT devices.
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Chapter 6: XAUI PHY IP Core Optional PMA Control and Status Interface 6–15 Table 6–12. Optional Control and Status Signals—Soft IP Implementation Signal Name Direction Description rx_syncstatus[7:0] Output Synchronization indication. RX synchronization is indicated on the rx_syncstatus port of each channel. The rx_syncstatus signal is 2 bits per channel for a total of 8 bits per hard XAUI link. The rx_syncstatus signal is 1 bit per channel for a total of 4 bits per soft XAUI link.
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6–16 Chapter 6: XAUI PHY IP Core Optional PMA Control and Status Interface Table 6–13. Optional Control and Status Signals—Hard IP Implementation, Stratix IV GX Devices (Part 2 of 2) Signal Name Direction Description Output Received 10-bit code or data group has a disparity error. It is paired with rx_errdetect which is also asserted when a disparity error occurs. The rx_disperr signal is 2 bits wide per channel for a total of 8 bits per XAUI link.
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Chapter 6: XAUI PHY IP Core Register Interface and Register Descriptions 6–17 Register Interface and Register Descriptions The Avalon-MM PHY management interface provides access to the XAUI PHY IP Core PCS, PMA, and transceiver reconfiguration registers. Table 6–14 describes the signals that comprise the Avalon-MM PHY Management interface. Table 6–14. Avalon-MM PHY Management Interface Signal Name Direction Description Avalon-MM clock input.
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6–18 Chapter 6: XAUI PHY IP Core Register Interface and Register Descriptions Table 6–15. XAUI PHY IP Core Registers (Part 2 of 5) Word Addr Bits R/W Register Name Description Reset Control Registers–Automatic Reset Controller 0x041 0x042 [31:0] reset_ch_bitmask Bit mask for reset registers at addresses 0x042 and 0x044. The default value is all 1s. Channel can be reset when bit = 1.
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Chapter 6: XAUI PHY IP Core Register Interface and Register Descriptions 6–19 Table 6–15. XAUI PHY IP Core Registers (Part 3 of 5) Word Addr 0x083 Bits R/W [31:4] — [3:0] RW Register Name Description Reserved invpolarity[3:0] — Inverts the polarity of corresponding bit on the TX interface. Bit 0 maps to lane 0 and so on. To block: Serializer.
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6–20 Chapter 6: XAUI PHY IP Core Register Interface and Register Descriptions Table 6–15. XAUI PHY IP Core Registers (Part 4 of 5) Word Addr Bits [31:8] R/W — Description Reserved — Indicates a RX phase compensation FIFO overflow or underrun condition on the corresponding lane. Reading the phase_comp_fifo_error[3: value of the phase_comp_fifo_error register clears the 0] bits.
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Chapter 6: XAUI PHY IP Core Dynamic Reconfiguration for Arria II GX, Cyclone IV GX, HardCopy IV GX, and Stratix IV GX 6–21 Table 6–15. XAUI PHY IP Core Registers (Part 5 of 5) Word Addr 0x089 Bits R/W [31:3] — [2:0] Register Name Reserved R, sticky Description — Indicates a TX phase compensation FIFO overflow or underrun condition on the corresponding lane. Reading the phase_comp_fifo_error[2: value of the phase_comp_fifo_error register clears the bits.
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6–22 Chapter 6: XAUI PHY IP Core Dynamic Reconfiguration for Arria V, Cyclone V and Stratix V Devices Table 6–16 describes the signals in the reconfiguration interface. If your XAUI PHY IP Core includes a single transceiver quad, these signals are internal to the core. If your design uses more than one quad, the reconfiguration signals are external. Table 6–16.
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Chapter 6: XAUI PHY IP Core Simulation Files and Example Testbench 6–23 Assignment Editor. In this example, the pma_bonding_master was originally assigned to physical channel 1. (The original assignment could also have been to physical channel 4.) The to parameter reassigns the pma_bonding_master to the Interlaken instance name. You must substitute the instance name from your design for the instance name shown in quotation marks Example 6–3.
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6–24 Altera Transceiver PHY IP Core User Guide Chapter 6: XAUI PHY IP Core Simulation Files and Example Testbench November 2012 Altera Corporation
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7. Interlaken PHY IP Core Interlaken is a high speed serial communication protocol for chip-to-chip packet transfers. The Altera Interlaken PHY IP Core implements Interlaken Protocol Specification, Rev 1.2. It supports multiple instances, each with 1 to 24 lanes running at 10.3125 Gbps or greater in Arria V GZ and Stratix V devices. The key advantages of Interlaken are scalability and its low I/O count compared to earlier protocols such as SPI 4.2.
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7–2 Chapter 7: Interlaken PHY IP Core Device Family Support ■ Lane-based CRC32 ■ Disparity DC balancing f For more detailed information about the Interlaken transceiver channel datapath, clocking, and channel placement in Stratix V devices, refer to the “Interlaken” section in the Transceiver Configurations in Stratix V Devices chapter of the Stratix V Device Handbook.
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Chapter 7: Interlaken PHY IP Core General Parameters 7–3 5. Click Finish to generate your parameterized Interlaken PHY IP Core. General Parameters Table 7–2 describes the parameters that you can set on the General tab. Table 7–2. Interlaken PHY General Options (Part 1 of 2) Parameter Value Arria V GZ Stratix V Device family Datapath mode Duplex, RX, TX 3125 Mbps 5000 Mbps 6250 Mbps 6375 Mbps 10312.5 Mbps 12500 Mbps Custom Lane rate Number of lanes 1–24 Description Specifies the device family.
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7–4 Chapter 7: Interlaken PHY IP Core Optional Port Parameters Table 7–2. Interlaken PHY General Options (Part 2 of 2) Parameter Value Description Specifies the PLL type. CMU ATX PLL type 1 × Lane rate 2 × Lane rate 4 × Lane rate Base data rate The CMU PLL has a larger frequency range than the ATX PLL. The ATX PLL is designed to improve jitter performance and achieves lower channel-to-channel skew; however, it supports a narrower range of lane data rates and reference clock frequencies.
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Chapter 7: Interlaken PHY IP Core Interfaces 7–5 Interfaces Figure 7–2 illustrates the top-level signals of the Interlaken PHY IP Core. In Table 7–2, is the channel number so that the width of tx_data in 4-lane instantiation is [263:0]. Figure 7–2.
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7–6 Chapter 7: Interlaken PHY IP Core Avalon-ST TX Interface Avalon-ST TX Interface Table 7–4 lists the signals in the Avalon-ST TX interface. Table 7–4. Avalon-ST TX Signals (Part 1 of 3) Signal Name tx_parallel_data[63:0] Direction Input Description Avalon-ST data bus driven from the FPGA fabric to the TX PCS. This input should be synchronized to the tx_coreclkin clock domain. Indicates whether tx_parallel_data[63:0] represents control or data.
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Chapter 7: Interlaken PHY IP Core Avalon-ST TX Interface 7–7 Table 7–4. Avalon-ST TX Signals (Part 2 of 3) Signal Name Direction Description When asserted, indicates that the TX interface has exited the reset state and is ready for service. The tx_ready latency for the TX interface is 0. A 0 latency means that the TX FIFO can accept data on the same clock cycle that tx_ready is asserted. This output is synchronous to the phy_mgmt_clk clock domain.
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7–8 Chapter 7: Interlaken PHY IP Core Avalon-ST RX Interface Table 7–4. Avalon-ST TX Signals (Part 3 of 3) Signal Name Direction Description tx_user_clkout Output For single lane Interlaken links, tx_user_clkout is available when you do not create the optional tx_coreclkin. For Interlaken links with more than 1 lane, tx_coreclkin is required and tx_user_clkout cannot be used. tx_coreclkin must have a minimum frequency of the lane data rate divided by 67.
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Chapter 7: Interlaken PHY IP Core Avalon-ST RX Interface 7–9 Table 7–5. Avalon-ST RX Signals (Part 2 of 4) Signal Name Direction Description Indicates whether rx_parallel_data[63:0] represents control or data. When deasserted, rx_parallel_data[63:0] is a data word. When asserted, rx_paralleldata[63:0] is a control word. This output is synchronous to the rx_coreclkin clock domain.
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7–10 Chapter 7: Interlaken PHY IP Core Avalon-ST RX Interface Table 7–5. Avalon-ST RX Signals (Part 3 of 4) Signal Name rx_parallel_data[69] rx_parallel_data[70] Direction Output Output Description When asserted, indicates that the RX FIFO has found the first Interlaken synchronization word alignment pattern.
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Chapter 7: Interlaken PHY IP Core TX and RX Serial Interface 7–11 Table 7–5. Avalon-ST RX Signals (Part 4 of 4) Signal Name Direction Description When asserted, enables reading of data from the RX FIFO. This signal functions as a read enable. The RX interface has a ready latency of 1 cycle so that rx_paralleldata[63:0] and rx_paralleldata[65] are valid the cycle after rx_dataout_bp is asserted. Input rx_dataout_bp This output is synchronous to the rx_coreclkin clock domain.
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7–12 Chapter 7: Interlaken PHY IP Core Optional Clocks for Deskew Optional Clocks for Deskew Table 7–8 describes the optional clocks that you can create to reduce clock skew. Table 7–8. Serial Interface Signal Name tx_coreclkin rx_coreclkin Direction Description Input When enabled tx_coreclkin is available as input port which drives the write side of TX FIFO. Altera recommends using this clock to reduce clock skew. The minimum frequency is data rate/67.
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Chapter 7: Interlaken PHY IP Core Register Interface and Register Descriptions 7–13 Table 7–9. Avalon-MM PCS Management Interface (Part 2 of 2) Signal Name Direction phy_mgmt_writedata[31:0] Input phy_mgmt_readdata[31:0] Output Description Input data. Output data. phy_mgmt_write Input Write signal. phy_mgmt_read Input Read signal. phy_mgmt_waitrequest Output When asserted, indicates that the Avalon-MM slave interface is unable to respond to a read or write request.
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7–14 Chapter 7: Interlaken PHY IP Core Register Interface and Register Descriptions Table 7–10. Interlaken PHY Registers (Part 2 of 3) Word Addr Bits R/W Register Name Description Reset Controls –Manual Mode You can use the reset_fine_control register to create your own reset sequence. The reset control module, illustrated in Transceiver PHY Top-Level Modules, performs a standard reset sequence at power on and whenever the phy_mgmt_clk_reset is asserted. Bits [31:4, 0] are reserved.
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Chapter 7: Interlaken PHY IP Core Why Transceiver Dynamic Reconfiguration 7–15 Table 7–10. Interlaken PHY Registers (Part 3 of 3) Word Addr Bits R/W Register Name Description Device Registers [27] 0x081 [25] RO RO rx_crc32_err rx_sync_lock Asserted by the CRC32 checker to indicate a CRC error in the corresponding RX lane. From block: CRC32 checker. Asserted by the frame synchronizer to indicate that 4 frame synchronization words have been received so that the RX lane is synchronized.
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7–16 Chapter 7: Interlaken PHY IP Core Dynamic Transceiver Reconfiguration Interface Dynamic Transceiver Reconfiguration Interface Table 7–11 describes the signals in the reconfiguration interface. This interface uses the Avalon-MM PHY Management interface clock. Table 7–11. Reconfiguration Interface Signal Name reconfig_to_xcvr [(70)-1:0] reconfig_from_xcvr [(46)-1:0] Direction Description Input Reconfiguration signals from the Transceiver Reconfiguration Controller.
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8. PHY IP Core for PCI Express (PIPE) The Altera PHY IP Core for PCI Express (PIPE) implements physical coding sublayer (PCS) and physical media attachment (PMA) modules for Gen1, Gen2, and Gen3 data rates. The Gen1 and Gen2 datapaths are compliant to the Intel PHY Interface for PCI Express (PIPE) Architecture PCI Express 2.0 specification. The Gen3 datapath is compliant to the PHY Interface for the PCI Express Architecture PCI Express 3.0 specification.
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8–2 Chapter 8: PHY IP Core for PCI Express (PIPE) Device Family Support Figure 8–2.
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Chapter 8: PHY IP Core for PCI Express (PIPE) Parameterizing the PHY IP Core for PCI Express (PIPE) 8–3 Parameterizing the PHY IP Core for PCI Express (PIPE) Complete the following steps to configure the PHY IP Core for PCI Express in the MegaWizard Plug-In Manager: 1. For Which device family will you be using?, select Arria V GZ or Stratix V. 2. Click Installed Plug-Ins > Interfaces > PCI Express > PHY IP Core for PCI Express (PIPE) v12.1. 3.
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8–4 Chapter 8: PHY IP Core for PCI Express (PIPE) General Options Parameters Table 8–2. PHY IP Core for PCI Express General Options (Part 2 of 2) Name Value Description Specifies the width of the interface between the PHY MAC and PHY (PIPE).The following options are available: FPGA transceiver width 8, 16, 32 ■ Gen1: 8 or 16 bits ■ Gen2: 16 bits ■ Gen3: 32 bits Using the Gen1 16-bit interface reduces the required clock frequency by half at the expense of extra FPGA resources.
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Chapter 8: PHY IP Core for PCI Express (PIPE) Interfaces 8–5 Interfaces This section describes interfaces of the PHY IP Core for PCI Express (PIPE). It includes Figure 8–3 illustrates the top-level pinout of the PHY IP Core for PCI Express PHY. The port descriptions use the following variables to represent parameters: ■ —The number of lanes ■ —The total deserialization factor from the input pin to the PHY MAC interface. ■ ~~—The symbols size.~~
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8–6 Chapter 8: PHY IP Core for PCI Express (PIPE) PIPE Input Data from the PHY MAC PIPE Input Data from the PHY MAC Table 8–3 describes the PIPE input signals. These signals are driven from the PHY MAC to the PCS. This interface is compliant to the appropriate PIPE interface specification. f For more information about the Avalon-ST protocol, including timing diagrams, refer to the Avalon Interface Specifications. Table 8–3.
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Chapter 8: PHY IP Core for PCI Express (PIPE) PIPE Input Data from the PHY MAC 8–7 Table 8–3. Avalon-ST TX Inputs (Part 2 of 3) Signal Name Dir Description Gen1 and Gen2 This signal requests the PHY to change its power state to the specified state.
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8–8 Chapter 8: PHY IP Core for PCI Express (PIPE) PIPE Input Data from the PHY MAC Table 8–3. Avalon-ST TX Inputs (Part 3 of 3) Signal Name Dir Description Gen1 and Gen2 When asserted high, the electrical idle state is inferred instead of being identified using analog circuitry to detect a device at the other end of the link.
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Chapter 8: PHY IP Core for PCI Express (PIPE) PIPE Output Data to the PHY MAC 8–9 PIPE Output Data to the PHY MAC Table 8–5 describes the PIPE output signals. These signals are driven from the PCS to the PHY MAC. This interface is compliant to the appropriate PIPE interface specification. Table 8–5. Avalon-ST RX Inputs (Part 1 of 2) Signal Name Dir Description This is RX parallel data driven from the PCS to the MAC PHY.
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8–10 Chapter 8: PHY IP Core for PCI Express (PIPE) Clocks Table 8–5. Avalon-ST RX Inputs (Part 2 of 2) Signal Name Dir Description This signal encodes receive status and error codes for the receive data stream and receiver detection.
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Chapter 8: PHY IP Core for PCI Express (PIPE) Optional Status Interface 8–11 Table 8–6. Clock Ports Signal Name Direction A 100 MHz or 125 MHz clock used for the receiver detect circuitry. This clock can be derived from pll_ref_clk. Input fixedclk Description Generated in the PMA and driven to the MAC PHY interface. All data and status signals are synchronous to pipe_pclk. This clock has the following frequencies: Output pipe_pclk ■ Gen1: 62.
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8–12 Chapter 8: PHY IP Core for PCI Express (PIPE) Serial Data Interface Serial Data Interface Table 8–9 describes the differential serial TX and RX connections to FPGA pins. Table 8–9. Transceiver Differential Serial Interface Signal Name Direction rx_serial_data[-1:0] Input tx_serial_data[-1:0] Output Description Receiver differential serial input data, is the number of lanes. Transmitter differential serial output data is the number of lanes.
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Chapter 8: PHY IP Core for PCI Express (PIPE) Register Interface and Register Descriptions 8–13 Figure 8–5 provides a high-level view of this hardware. In Figure 8–5, modules shown in white are hard logic. Modules shown in gray are soft logic. Figure 8–5.
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8–14 Chapter 8: PHY IP Core for PCI Express (PIPE) Register Interface and Register Descriptions Table 8–10. Avalon-MM PHY Management Interface (Part 2 of 2) Signal Name Direction Input phy_mgmt_read phy_mgmt_waitrequest Output Description Read signal. When asserted, indicates that the Avalon-MM slave interface is unable to respond to a read or write request. When asserted, control signals to the Avalon-MM slave interface must remain constant.
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Chapter 8: PHY IP Core for PCI Express (PIPE) Register Interface and Register Descriptions 8–15 Table 8–11. PCI Express PHY (PIPE) IP Core Registers (Part 2 of 4) Word Addr Bits R/W Register Name Description Reset Controls –Manual Mode [31:0] RW reset_fine_control You can use the reset_fine_control register to create your own reset sequence.
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8–16 Chapter 8: PHY IP Core for PCI Express (PIPE) Register Interface and Register Descriptions Table 8–11. PCI Express PHY (PIPE) IP Core Registers (Part 3 of 4) Word Addr Bits R/W Register Name Description PCS for PCI Express 0x080 [31:0] RW [31:6] R Reserved R rx_bitslipboundary selectout [5:1] 0x081 Lane or group number Specifies lane or group number for indirect addressing, which is used for all PCS control and status registers.
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Chapter 8: PHY IP Core for PCI Express (PIPE) Link Equalization for Gen3 Data Rate 8–17 Table 8–11. PCI Express PHY (PIPE) IP Core Registers (Part 4 of 4) Word Addr Bits R/W Register Name [31:20] R Reserved [19:16] R rx_rlv [15:12] R rx_patterndetect Description — When set, indicates a run length violation. From block: Word aligner. When set, indicates that RX word aligner has achieved synchronization. From block: Word aligner.
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8–18 Chapter 8: PHY IP Core for PCI Express (PIPE) Link Equalization for Gen3 Data Rate Phase 0 Phase 0 includes the following steps: 1. Upstream component enters Phase 0 of equalization during Recovery.Rcvrconfig by sending EQ TS2 training sets with starting presets for the downstream component. EQ TS2 training sets may be sent at 2.5 GT/s or 5 GT/s. 2. The downstream component enters Phase 0 of equalization after exiting Recovery.Speed at 8 GT/s.
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Chapter 8: PHY IP Core for PCI Express (PIPE) Link Equalization for Gen3 Data Rate 8–19 The tuning sequence typically includes the following steps: 1. The Endpoint receives the starting presets from the Phase 2 training sets sent by the Root Port. 2. The circuitry in the Endpoint receiver determines the BER and calculates the next set of transmitter coefficients using FS and LF and embeds this information in the Training Sets for the Link Partner to apply to its transmitter.
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8–20 Chapter 8: PHY IP Core for PCI Express (PIPE) Enabling Dynamic PMA Tuning for PCIe Gen3 Enabling Dynamic PMA Tuning for PCIe Gen3 “Section 4.2.3 Link Equalization Procedure for 8.0 GT/s Data Rate” in the PCI Express Base Specification, Rev. 3.0 provides detailed information about the four-stage link equalization procedure. However, in some instances you may want to override the specified four-stage link equalization procedure to dynamically tune PMA settings.
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Chapter 8: PHY IP Core for PCI Express (PIPE) Simulation Files and Example Testbench 8–21 Table 8–12 describes the signals in the reconfiguration interface. This interface uses the Avalon-MM PHY Management interface clock. Table 8–12. Reconfiguration Interface Signal Name reconfig_to_xcvr [70-1:0] reconfig_from_xcvr [46-1:0] Direction Description Input Reconfiguration signals from the Transceiver Reconfiguration Controller. grows linearly with the number of reconfiguration interfaces.
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~~8–22 Altera Transceiver PHY IP Core User Guide Chapter 8: PHY IP Core for PCI Express (PIPE) Simulation Files and Example Testbench November 2012 Altera Corporation~~
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9. Custom PHY IP Core The Altera Custom PHY IP Core is a generic PHY that you can customize for use in Arria V, Cyclone V, or Stratix V FPGAs. You can connect your application’s MAC-layer logic to the Custom PHY to transmit and receive data at rates of 0.611–6.5536 Gbps for Arria V GX devices, 0.611–10.3125 Gbps in Arria V GT devices, 0.622–9.8304 Gbps in Arria V GZ devices, 0.611–3.125 Gbps for Cyclone V GX devices, 0.611–5.000 Gbps for Cyclone V GT devices, and 0.622–11.0 Gbps for Stratix V devices.
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~~9–2 Chapter 9: Custom PHY IP Core Device Family Support Figure 9–1 illustrates the top-level signals and modules of the Custom PHY. Figure 9–1.~~
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Chapter 9: Custom PHY IP Core Parameterizing the Custom PHY 9–3 Parameterizing the Custom PHY Complete the following steps to configure the Custom PHY IP Core in the MegaWizard Plug-In Manager: 1. For Which device family will you be using?, select Stratix V. 2. Click Installed Plug-Ins > Interfaces > Transceiver PHY > Custom PHY v12.1. 3. Use the tabs on the MegaWizard Plug-In Manager to select the options required for the protocol. 4. Refer to the following topics to learn more about the parameters: a.
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9–4 Chapter 9: Custom PHY IP Core General Options Parameters Table 9–2. Custom PHY General Options (Part 2 of 4) Name Value Description Select ×1 to use separate clock sources for each channel. (This option is available for Cyclone V and Arria V devices.) Select ×N to use the same clock source for up to 6 channels in a single transceiver bank, resulting in reduced clock skew. You must use contiguous channels when you select ×N bonding.
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Chapter 9: Custom PHY IP Core General Options Parameters 9–5 Table 9–2. Custom PHY General Options (Part 3 of 4) Name Value Description The CMU PLL is available for Arria V and Cyclone V devices. For Stratix V devices, you can select either the CMU or ATX PLL. The CMU PLL has a larger frequency range than the ATX PLL. The ATX PLL is designed to improve jitter performance and achieves lower channel-to-channel skew; however, it supports a narrower range of data rates and reference clock frequencies.
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9–6 Chapter 9: Custom PHY IP Core General Options Parameters Table 9–2. Custom PHY General Options (Part 4 of 4) Name Enable Avalon data interfaces and bit reversal Value Description On/Off When you turn this option On, the order of symbols is changed. This option is typically required if you are planning to import your Custom PHY IP Core into a Qsys system. When On, the automatic reset controller initiates the reset sequence for the transceiver.
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Chapter 9: Custom PHY IP Core Word Alignment Parameters 9–7 Word Alignment Parameters The word aligner restores word boundaries of received data based on a predefined alignment pattern. This pattern can be 7, 8, 10, 16, 20, or 32 bits long. The word alignment module searches for a programmed pattern to identify the correct boundary for the incoming stream. Table 9–4 lists the settings available on the Word Aligner tab. Table 9–4.
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9–8 Chapter 9: Custom PHY IP Core Rate Match FIFO Parameters Table 9–5 provides more information about the word alignment function. Table 9–5. Word Aligner Options PMA-PCS Interface Width (bits) Word Alignment Mode Word Alignment Pattern Length (bits) 8 Manual alignment 8, 16 User-controlled signal starts alignment process. Alignment occurs once unless signal is re-asserted. User-controlled signal starts alignment process. Alignment occurs once unless signal is re-asserted.
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Chapter 9: Custom PHY IP Core 8B/10B Encoder and Decoder Parameters 9–9 Table 9–6. Rate Match FIFO Options (Part 2 of 2) Name Value Rate match insertion/deletion -ve disparity pattern 0010111100 0101111100 Create optional rate match FIFO status ports On/Off Description Enter a 10-bit skip pattern (bits 10–19) and a 10-bit control pattern (bits 0–9). The skip pattern must have neutral disparity.
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9–10 Chapter 9: Custom PHY IP Core Byte Order Parameters 1 You cannot enable Rate Match FIFO when your application requires byte ordering. Because the rate match function inserts and deletes idle characters, it may shift the SOP to a different byte lane. Table 9–8. Byte Order Options (Part 1 of 2) Name Value Description Turn this option on if your application uses serialization to create a datapath that is larger than 1 symbol.
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Chapter 9: Custom PHY IP Core Byte Order Parameters 9–11 Table 9–8. Byte Order Options (Part 2 of 2) Name Value Description Specifies the pattern that identifies the SOP. For 16-bit byte ordering pattern you must include a 2-bit pad so that the pattern entered is in the following format: 00 00 .
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9–12 Chapter 9: Custom PHY IP Core PLL Reconfiguration Parameters PLL Reconfiguration Parameters Table 9–9 lists the PLL Recon figurations options. For more information about transceiver reconfiguration registers, refer to Transceiver Reconfiguration Controller IP Core. Table 9–9. PLL Reconfigurations Name Allow PLL Reconfiguration Value On/Off Description You must enable this option if you plan to reconfigure the PLLs in your design. This option is also required to simulate PLL reconfiguration.
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Chapter 9: Custom PHY IP Core Analog Parameters 9–13 Table 9–9. PLL Reconfigurations Name Value Description Channel Interface Turn this option on to enable PLL and datapath dynamic reconfiguration. When you select this option, the width of tx_parallel_data and rx_parallel_data buses increases in the following way.
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~~9–14 Chapter 9: Custom PHY IP Core Interfaces Table 9–10. Presets for Ethernet Protocol (Part 2 of 2) Parameter Name GIGE-1.25 Gbps GIGE-2.~~
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~~Chapter 9: Custom PHY IP Core Data Interfaces ■ 9–15~~
~~—The number of PLLs Figure 9–2.~~
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9–16 Chapter 9: Custom PHY IP Core Data Interfaces Table 9–11. Avalon-ST TX Interface Signals Signal Name Direction Description tx_datak[(/)-1:0] Input Data and control indicator for the received data. When 0, indicates that tx_data is data, when 1, indicates that tx_data is control. tx_forcedisp[(/~~)-1:0] Input When asserted, this control signal enables disparity to be forced on the TX channel.~~
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Chapter 9: Custom PHY IP Core Clock Interface 9–17 Clock Interface Table 9–14 describes optional and required clocks for the Custom PHY. The input reference clock, pll_ref_clk, drives a PLL inside the PHY-layer block, and a PLL output clock, rx_clkout (described in Avalon-ST RX Interface Signals) is used for all data, command, and status inputs and outputs. Table 9–14. Clock Signals Signal Name Direction Description pll_ref_clk Input Reference clock for the PHY PLLs. Frequency range is 50–700 MHz.
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9–18 Chapter 9: Custom PHY IP Core Optional Reset Control and Status Interface Table 9–15. Serial Interface and Status Signals (Part 2 of 2) Signal Name Direction Signal Name Output Signal threshold detect indicator required for the PCI Express protocol. When asserted, it indicates that the signal present at the receiver input buffer is above the programmed signal detection threshold value. Input Used for manual control of bit slipping.
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Chapter 9: Custom PHY IP Core Register Interface and Register Descriptions 9–19 Register Interface and Register Descriptions The Avalon-MM PHY management interface provides access to the Custom PHY PCS and PMA registers, resets, error handling, and serial loopback controls. You can use an embedded controller acting as an Avalon-MM master to send read and write commands to this Avalon-MM slave interface. Figure 9–3 provides a high-level view of this hardware. Figure 9–3.
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9–20 Chapter 9: Custom PHY IP Core Register Interface and Register Descriptions Table 9–17. Avalon-MM PHY Management Interface (Part 2 of 2) Signal Name Direction Description Output Output data. phy_mgmt_write Input Write signal. phy_mgmt_read Input Read signal. phy_mgmt_readdata[31:0] phy_mgmt_waitrequest Output When asserted, indicates that the Avalon-MM slave interface is unable to respond to a read or write request.
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Chapter 9: Custom PHY IP Core Register Interface and Register Descriptions 9–21 Table 9–18. Custom PHY IP Core Registers (Part 2 of 3) Word Addr Bits R/W Register Name Description Reset Controls –Manual Mode [31:0] RW reset_fine_control You can use the reset_fine_control register to create your own reset sequence.
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9–22 Chapter 9: Custom PHY IP Core Register Interface and Register Descriptions Table 9–18. Custom PHY IP Core Registers (Part 3 of 3) Word Addr Bits R/W Register Name Description Custom PCS 0x080 Lane or group number Specifies lane or group number for indirect addressing, which is used for all PCS control and status registers. For variants that stripe data across multiple lanes, this is the logical group number. For non-bonded applications, this is the logical lane number.
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Chapter 9: Custom PHY IP Core Dynamic Reconfiguration 9–23 Dynamic Reconfiguration As silicon progresses towards smaller process nodes, circuit performance is affected more by variations due to process, voltage, and temperature (PVT). These process variations result in analog voltages that can be offset from required ranges. The calibration performed by the dynamic reconfiguration interface compensates for variations due to PVT.
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9–24 Chapter 9: Custom PHY IP Core Simulation Files and Example Testbench Assignment Editor. In this example, the pma_bonding_master was originally assigned to physical channel 1. (The original assignment could also have been to physical channel 4.) The to parameter reassigns the pma_bonding_master to the Custom PHY instance name. You must substitute the instance name from your design for the instance name shown in quotation marks Example 9–2.
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10. Low Latency PHY IP Core The Altera Low Latency PHY IP Core receives and transmits differential serial data, recovering the RX clock from the RX input stream. The PMA connects to a simplified PCS, which contains a phase compensation FIFO.
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10–2 Chapter 10: Low Latency PHY IP Core Performance and Resource Utilization - Need Update Table 10–1 shows the level of support offered by the Low Latency PHY IP Core for Altera device families. Table 10–1.
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Chapter 10: Low Latency PHY IP Core General Options Parameters 10–3 1. For Which device family will you be using?, select Stratix V. 2. Click Installed Plug-Ins > Interfaces > Transceiver PHY >Low Latency PHY v12.1. 3. Use the tabs on the MegaWizard Plug-In Manager to select the options required for the protocol. 4. Refer to the following topics to learn more about the parameters: a. General Options Parameters b. Additional Options Parameters c. PLL Reconfiguration Parameters d. Analog Parameters 5.
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10–4 Chapter 10: Low Latency PHY IP Core General Options Parameters Table 10–3. Low Latency PHY General Options Name Value Description Select ×N to use the same clock source for up to 6 channels in a single transceiver bank, resulting in reduced clock skew. You must use contiguous channels when you select ×N bonding. In addition, you must place logical channel 0 in either physical channel 1 or 4. Physical channels 1 and 4 are indirect drivers of the ×N clock network.
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Chapter 10: Low Latency PHY IP Core Additional Options Parameters 10–5 Table 10–4 lists Standard and 10G datapath widths for the FPGA fabric-transceiver interface, the PCS-PMA interface, and the resulting frequencies for the tx_clkout and rx_clkout parallel clocks.
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10–6 Chapter 10: Low Latency PHY IP Core Additional Options Parameters Table 10–5 describes the options available on the Additional Options tab. Table 10–5. Additional Options (Part 1 of 2) Name Enable tx_coreclkin Value Description On/Off When you turn this option on, tx_coreclkin connects to the write clock of the TX phase compensation FIFO and you can clock the parallel TX data generated in the FPGA fabric using this port.
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Chapter 10: Low Latency PHY IP Core PLL Reconfiguration Parameters 10–7 Table 10–5. Additional Options (Part 2 of 2) Name Value Description This option is turned on by default. When On, the embedded reset controller initiates the reset sequence when it receives a positive edge on the phy_mgmt_clk_reset input signal.
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10–8 Chapter 10: Low Latency PHY IP Core PLL Reconfiguration Parameters Table 10–6. PLL Reconfigurations (Part 2 of 2) Name CDR PLL input clock source Value Description 0–3 Specifies the index for the TX PLL input clock that should be instantiated at startup. Logical index 0 corresponds to input clock 0 and so on. TX PLL (0–3) (Refer to Low Latency PHY General Options for a detailed explanation of these parameters.
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Chapter 10: Low Latency PHY IP Core Analog Parameters 10–9 Analog Parameters For analog parameters refer to Analog Settings for Stratix V Devices. Interfaces Figure 10–2 illustrates the top-level signals of the Custom PHY IP Core. The variables in Figure 10–2 represent the following parameters: ■ —The number of lanes ■ —The width of the FPGA fabric to transceiver interface per lane Figure 10–2.
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10–10 Chapter 10: Low Latency PHY IP Core Data Interfaces Data Interfaces Table 10–7 describes the signals in the Avalon-ST interface. This interface drives Avalon-ST TX and RX data to and from the FPGA fabric. These signals are named from the point of view of the MAC so that the TX interface is an Avalon-ST sink interface and the RX interface is an Avalon-ST source. Table 10–7.
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Chapter 10: Low Latency PHY IP Core Optional Status Interface 10–11 Optional Status Interface Table 10–9 describes the signals that comprise the optional status interface. Table 10–9. Optional Status Interface Signal Name Direction Description Output When asserted, indicates that the RX CDR is locked to incoming data. This signal is optional. If latency is not critical, you can read the value of this signal from the Rx_is_lockedtodata register.
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10–12 Chapter 10: Low Latency PHY IP Core Optional Reset Control and Status Interface Optional Reset Control and Status Interface Table 10–11 describes the signals in the optional reset control and status interface. These signals are available if you do not enable the embedded reset controller. For more information including timing diagrams, refer to Transceiver Reset Control in Stratix V Devices in volume 2 of the Stratix V Device Handbook. Table 10–11.
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Chapter 10: Low Latency PHY IP Core Register Interface and Register Descriptions 10–13 Table 10–12 describes the signals in the PHY Management interface. Table 10–12. Avalon-MM PHY Management Interface Signal Name Direction Description phy_mgmt_clk Input Avalon-MM clock input.
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10–14 Chapter 10: Low Latency PHY IP Core Dynamic Reconfiguration Table 10–13. Low Latency PHY IP Core Registers (Part 2 of 2) Word Addr Bits R/W Register Name Description PMA Control and Status Registers 0x061 [31:0] RW phy_serial_loopback Writing a 1 to channel puts channel in serial loopback mode. For information about pre- or post-CDR serial loopback modes, refer to Loopback Modes.
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Chapter 10: Low Latency PHY IP Core Simulation Files and Example Testbench 10–15 Avalon-MM slave interface which connects to the Transceiver Reconfiguration Controller IP Core. Conversely, you cannot connect the three channels that share an Avalon-MM interface to different Transceiver Reconfiguration Controller IP Cores. Doing so causes a Fitter error. For more information, refer to Transceiver Reconfiguration Controller to PHY IP Connectivity.
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~~10–16 Altera Transceiver PHY IP Core User Guide Chapter 10: Low Latency PHY IP Core Simulation Files and Example Testbench November 2012 Altera Corporation~~
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11. Deterministic Latency PHY IP Core The Altera Deterministic Latency PHY IP Core targets protocols that require a datapath with deterministic latency. Deterministic latency enables accurate delay measurements and known timing for the transmit (TX) and receive (RX) datapaths as required in applications such as wireless communication systems, emerging Ethernet standards, and test and measurement equipment.
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11–2 Chapter 11: Deterministic Latency PHY IP Core Auto-Negotiation The data that the Deterministic Latency PHY receives data on its FPGA fabric interface employs the Avalon Streaming (Avalon-ST) protocol to transmit and receive data. The Avalon-ST protocol is a simple protocol designed for driving high bandwidth, low latency, unidirectional data. The Deterministic Latency PHY IP Core also includes an Avalon Memory-Mapped (Avalon-MM) interface to access control and status registers.
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Chapter 11: Deterministic Latency PHY IP Core Achieving Deterministic Latency 11–3 Achieving Deterministic Latency Figure 11–2 illustrates the TX and RX channels when configured as a wireless basestation communicating to a remote radio head (RRH) using a CPRI or OBSAI interface. Figure 11–2 also provides an overview of the calculations that guarantee deterministic delay.
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11–4 Chapter 11: Deterministic Latency PHY IP Core Achieving Deterministic Latency 1 Systems that require multiple PLLs in a single transceiver block must use a delay estimate FIFO to determine delay estimates and the required phase adjustments. Figure 11–3 illustrates the use of TX feedback and an external VCXO for clock jitter cleanup. It shows the following three delay variables: ■ T1—The delay from user logic to FPGA pin. Quartus II software includes this delay in its timing models.
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Chapter 11: Deterministic Latency PHY IP Core Delay Estimation Logic 11–5 Delay Estimation Logic This section provides the equations to calculate delays when the Deterministic Latency PHY IP Core implements CPRI protocol. CPRI defines the radio base station interface between network radio equipment controllers (REC) and radio equipment (RE) components.
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11–6 Chapter 11: Deterministic Latency PHY IP Core Delay Estimation Logic Delay Numbers Table 11–2 shows the total latency through the TX PCS in parallel clock cycles with the byte serializer/deserializer turned off. The TX compensation FIFO is in register mode. Table 11–2. TX PCS Total Latency TX Phase Comp FIFO PCS Datapath Width Serializer 8B/10B Bitslip Total TX Parallel Clock Cycles Byte Serializer/Deserializer Turned Off 8 bits 1.0 1.0 1.0 0 3.0 16 bits 1.0 1.0 1.0 0 3.
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Chapter 11: Deterministic Latency PHY IP Core Device Family Support 11–7 Device Family Support IP cores provide either final or preliminary support for target Altera device families. These terms have the following definitions: ■ Final support—Verified with final timing models for this device. ■ Preliminary support—Verified with preliminary timing models for this device. Table 11–5 shows the level of support offered by the Deterministic Latency PHY IP Core for Altera device families. Table 11–5.
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11–8 Chapter 11: Deterministic Latency PHY IP Core General Options Parameters General Options Parameters The General Options tab allows you to set the basic parameters of your transceiver PHY. Table 11–6 lists the settings available on the General Options tab. Table 11–6.
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Chapter 11: Deterministic Latency PHY IP Core General Options Parameters 11–9 Table 11–6. General Options (Part 2 of 2) Name Input clock frequency Enable tx_clkout feedback path for TX PLL Value Description Data rate/20 Data rate/10 Data rate/8 Data rate/5 Data rate/4 Data rate/2.5 Data rate/2 Data rate/1.25 Data rate/1 This is the reference clock for the PHY PLL. The available options are based on the Base data rate specified.
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11–10 Chapter 11: Deterministic Latency PHY IP Core Additional Options Parameters Additional Options Parameters Table 11–8 lists the settings available on the Additional Options tab. Table 11–8. Additional Options (Part 1 of 2) Name Value Description The word aligner restores word boundaries of received data based on a predefined alignment pattern. The word aligner automatically performs an initial alignment to the specified word pattern after reset deassertion.
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Chapter 11: Deterministic Latency PHY IP Core PLL Reconfiguration Parameters 11–11 Table 11–8. Additional Options (Part 2 of 2) Name Value Description On/Off TX bitslip is enabled whenever the word aligner is in Manual alignment mode. The TX bitslipper uses the value of bitslipboundarselect[4:0] to compensate for bits slipped on the RX datapath to achieve deterministic latency.
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11–12 Chapter 11: Deterministic Latency PHY IP Core Analog Parameters Table 11–9. PLL Reconfiguration Options Name Value Description Number of reference clocks 1–5 Specifies the number of input reference clocks. More than one reference clock may be required if your design reconfigures channels to run at multiple frequencies. Main TX PLL logical index 0–3 Specifies the index for the TX PLL that should be instantiated at startup. Logical index 0 corresponds to TX PLL0, and so on.
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Chapter 11: Deterministic Latency PHY IP Core Interfaces 11–13 Interfaces Figure 11–4 illustrates the top-level signals of the Deterministic Latency PHY IP Core. The variables in Figure 11–4 represent the following parameters: ■ —The number of lanes ■ —The width of the FPGA fabric to transceiver interface per lane ■ ~~— The symbol size ■~~
~~—The number of PLLs Figure 11–4.~~
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11–14 Chapter 11: Deterministic Latency PHY IP Core Data Interfaces Data Interfaces Table 11–10 describes the signals in the Avalon-ST input interface. These signals are driven from the MAC to the PCS. This is an Avalon sink interface. f For more information about the Avalon-ST protocol, including timing diagrams, refer to the Avalon Interface Specifications. Table 11–10.
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Chapter 11: Deterministic Latency PHY IP Core Data Interfaces 11–15 Table 11–12 describes the signals in the Avalon-ST output interface. These signals are driven from the PCS to the MAC. This is an Avalon source interface Table 11–12. Avalon-ST RX Interface Signal Name Direction Description rx_parallel_data[()-1:0] Output This is RX parallel data driven from the Deterministic Latency PHY IP Core.
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11–16 Chapter 11: Deterministic Latency PHY IP Core Clock Interface Table 11–14 describes the differential serial data interface and the status signals for the transceiver serial data interface. Table 11–14. Serial Interface and Status Signals Signal Name (1) Direction rx_serial_data[-1:0] Input tx_serial_data[-1:0] Output Signal Name Receiver differential serial input data. Transmitter differential serial output data. Note to Table 11–14: (1) is the number of lanes.
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Chapter 11: Deterministic Latency PHY IP Core Optional Reset Control and Status Interfaces 11–17 Table 11–16. Serial Interface and Status Signals (Part 2 of 2) (1) Signal Name Direction Signal Name Output When asserted, indicates that a received 10-bit code group has an 8B/10B code violation or disparity error. rx_syncstatus[((/~~)-1:0] Output Indicates presence or absence of synchronization on the RX interface.~~
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11–18 Chapter 11: Deterministic Latency PHY IP Core Register Interface and Register Descriptions Register Interface and Register Descriptions The Avalon-MM PHY management interface provides access to the Deterministic Latency PHY PCS and PMA registers that control the TX and RX channels, the PMA powerdown and PLL registers, and loopback modes. Figure 11–5 illustrates the role of the PHY Management module in the Deterministic Latency PHY. Figure 11–5.
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Chapter 11: Deterministic Latency PHY IP Core Register Interface and Register Descriptions 11–19 Table 11–18. Avalon-MM PHY Management Interface (Part 2 of 2) Signal Name Direction Description Output Output data. phy_mgmt_write Input Write signal. phy_mgmt_read Input Read signal. phy_mgmt_readdata[31:0] Output phy_mgmt_waitrequest When asserted, indicates that the Avalon-MM slave interface is unable to respond to a read or write request.
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11–20 Chapter 11: Deterministic Latency PHY IP Core Register Interface and Register Descriptions Table 11–19. Deterministic Latency PHY IP Core Registers (Part 2 of 3) Word Addr Bits R/W Register Name Description Reset Controls –Manual Mode 0x044 [31:0] RW reset_fine_control You can use the reset_fine_control register to create your own reset sequence. In manual mode, only the TX reset occurs automatically at power on and when the phy_mgmt_clk_reset is asserted.
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Chapter 11: Deterministic Latency PHY IP Core Dynamic Reconfiguration 11–21 Table 11–19. Deterministic Latency PHY IP Core Registers (Part 3 of 3) Word Addr 0x082 Bits R/W Register Name [31:1] R [0] RW Reserved [31:6] RW pcs8g_tx_control [5:1] RW tx_bitslipboundary_select [0] RW tx_invpolarity [31:1] RW Reserved. pcs8g_tx_status 0x083 Description Reserved. — Reserved. Sets the number of bits that the TX bit slipper needs to slip. To block: Word aligner.
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11–22 Chapter 11: Deterministic Latency PHY IP Core Channel Placement and Utilization Avalon-MM slave interface which connects to the Transceiver Reconfiguration Controller IP Core. Conversely, you cannot connect the three channels that share an Avalon-MM interface to different Transceiver Reconfiguration Controller IP Cores. Doing so causes a Fitter error. For more information, refer to Transceiver Reconfiguration Controller to PHY IP Connectivity. Example 11–1.
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Chapter 11: Deterministic Latency PHY IP Core Simulation Files and Example Testbench 11–23 Figure 11–6 shows the placement of transceiver banks in Arria V devices and indicates the channels that are not available. Figure 11–6.
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~~11–24 Altera Transceiver PHY IP Core User Guide Chapter 11: Deterministic Latency PHY IP Core Simulation Files and Example Testbench November 2012 Altera Corporation~~
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12. Stratix V Transceiver Native PHY IP Core The Stratix V Transceiver Native PHY IP Core provides direct access to all control and status signals of the transceiver channels. Unlike other PHY IP Cores, the Native PHY IP Core does not include an Avalon Memory-Mapped (Avalon-MM) interface. Instead, it exposes all signals directly as ports.
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12–2 Chapter 12: Stratix V Transceiver Native PHY IP Core Device Family Support In a typical design, the separately instantiated Transceiver PHY Reset Controller drives reset signals to Native PHY and receives calibration and locked status signal from the Native PHY. The Native PHY reconfiguration buses connect the external Transceiver Reconfiguration Controller for calibration and dynamic reconfiguration of the PLLs. You specify the initial configuration when you parameterize the IP core.
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Chapter 12: Stratix V Transceiver Native PHY IP Core Parameter Presets 12–3 Parameter Presets Presets allow you to specify a group of parameters to implement a particular protocol or application. If you apply a preset, the parameters with specific required values are set for you. When applied, the preset is in boldface and remains as such unless you change some of the preset parameters. Selecting a preset does not prevent you from changing any parameter to meet the requirements of your design.
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12–4 Chapter 12: Stratix V Transceiver Native PHY IP Core General Parameters General Parameters Table 12–2 lists the parameters available on the General Options tab. Note that you can enable the Standard PCS, the 10G PCS, or both if you intend to reconfigure between the two available PCS datapaths. Table 12–2. General and Datapath Options Name Device speed grade Message level for rule violations Range Description fastest–3_H3 Specifies the speed grade.
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Chapter 12: Stratix V Transceiver Native PHY IP Core PMA Parameters 12–5 PMA Parameters Table 12–3 describes the options available for the PMA. f For more information about the PMA, refer to the PMA Architecture section in the Transceiver Architecture in Stratix V Devices. Some parameters have ranges where the value is specified as Device Dependent. For such parameters, the possible range of frequencies and bandwidths depends on the device, speed grade, and other design characteristics.
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12–6 Chapter 12: Stratix V Transceiver Native PHY IP Core PMA Parameters TX PMA Parameters Table 12–4 describes the TX PMA options you can specify. f For more information about the TX CMU, ATX, and fractional PLLs, refer to the Stratix V PLLs section in Transceiver Architecture in Stratix V Devices. Table 12–4. TX PMA Parameters Parameter Range Description On/Off When you turn this option On, you can dynamically reconfigure the PLL to use a different reference clock input.
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Chapter 12: Stratix V Transceiver Native PHY IP Core PMA Parameters 12–7 TX PLL Table 12–5 allows you to define multiple TX PLLs for your Native PHY. The Native PHY GUI provides a separate tab for each TXPLL. Table 12–5. TX PLL Parameters Parameter PLL type Range CMU, ATX Description You can select either the CMU or ATX PLL. the CMU PLL has a larger frequency range than the ATX PLL.
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12–8 Chapter 12: Stratix V Transceiver Native PHY IP Core PMA Parameters RX CDR Options Table 12–6 describes the RX CDR options you can specify. f For more information about the CDR circuitry, refer to the Receiver Clock Data Recovery Unit section in Clock Networks and PLLs in Stratix V Devices. Table 12–6. RX PMA Parameters Parameter Enable CDR dynamic reconfiguration Range Description On/Off When you turn this option On, you can dynamically change the reference clock input the CDR circuit.
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Chapter 12: Stratix V Transceiver Native PHY IP Core PMA Parameters 12–9 Table 12–7. RX PMA Parameters (Part 2 of 2) Parameter Range Description Enable tx_pma_qpipullup port (QPI) On/Off When you turn this option On, the core includes tx_pma_qpipullup control input port. This port is only used for QPI applications. Enable tx_pma_qpipulldn port (QPI) On/Off When you turn this option On, the core includes tx_pma_qpipulldn control input port. This port is only used for QPI applications.
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12–10 Chapter 12: Stratix V Transceiver Native PHY IP Core PMA Parameters Table 12–8. Latency for RX Deserialization in Stratix V Devices (Part 2 of 2) FPGA Fabric Interface Width Stratix V Latency in UI 20 bits 23 32 bits 35 40 bits 43 64 bits 99 80 bits 123 Table 12–9 lists the best- case latency for the LSB of the TX serializer for all supported interface widths for the PMA Direct datapath. Table 12–9.
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Chapter 12: Stratix V Transceiver Native PHY IP Core Standard PCS Parameters 12–11 Standard PCS Parameters Figure 12–3 shows the complete datapath and clocking for the Standard PCS. You use parameters available in the GUI to enable or disable the individual blocks in the Standard PCS. Figure 12–3.
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12–12 Chapter 12: Stratix V Transceiver Native PHY IP Core Standard PCS Parameters Table 12–11 describes the general and datapath options for the Standard PCS. Table 12–11. General and Datapath Parameters Parameter Range Description Specifies the protocol that you intend to implement with the Native PHY. The protocol mode selected guides the MegaWizard in identifying legal settings for the Standard PCS datapath.
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Chapter 12: Stratix V Transceiver Native PHY IP Core Standard PCS Parameters 12–13 f For more information refer to the Receiver Phase Compensation FIFO and Transmitter Phase Compensation FIFO sections in Transceiver Architecture in Stratix V Devices. Table 12–12. Phase Compensation FIFO Parameters Parameter Range Description The following 2 modes are possible: low_latency register_fifo TX FIFO mode ■ low_latency: This mode adds 3–4 cycles of latency to the TX datapath.
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12–14 Chapter 12: Stratix V Transceiver Native PHY IP Core Standard PCS Parameters Table 12–13. Byte Ordering Block Parameters (Part 2 of 2) Parameter Range Description Shows width of the pad that you must specify.
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Chapter 12: Stratix V Transceiver Native PHY IP Core Standard PCS Parameters 12–15 f For more information refer to the Byte Serializer and Byte Deserializer sections in Transceiver Architecture in Stratix V Devices. Table 12–14.
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12–16 Chapter 12: Stratix V Transceiver Native PHY IP Core Standard PCS Parameters f For more information refer to the Rate Match (Clock Rate Compensation) FIFO section in Transceiver Architecture in Stratix V Devices. Table 12–16. Rate Match FIFO Parameters Parameter Range Description On/Off When you turn this option On, the PCS includes a FIFO to compensate for the very small frequency differences between the local system clock and the RX recovered clock.
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Chapter 12: Stratix V Transceiver Native PHY IP Core Standard PCS Parameters 12–17 Table 12–17. Word Aligner and Bit-Slip Parameters (Part 2 of 2) Parameter Range Description Specifies one of the following 3 modes for the word aligner: RX word aligner mode bit_silp sync_sm manual RX word aligner pattern length 7,8,10,16,20,32 RX word aligner pattern (hex) User-specified ■ Bit_slip: You can use bit slip mode to shift the word boundary.
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12–18 Chapter 12: Stratix V Transceiver Native PHY IP Core Standard PCS Parameters Bit Reversal and Polarity Inversion These functions allow you to reverse bit order, byte order, and polarity to correct errors and to accommodate different layouts of data. Table 12–18 describes these parameters. Table 12–18.
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Chapter 12: Stratix V Transceiver Native PHY IP Core 10G PCS Parameters 12–19 10G PCS Parameters Figure 12–4 shows the complete datapath and clocking for the 10G PCS. You use parameters available in the GUI to enable or disable the individual blocks in the 10G PCS. Figure 12–4.
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12–20 Chapter 12: Stratix V Transceiver Native PHY IP Core 10G PCS Parameters Table 12–19 describes the general and datapath options for the 10G PCS. Table 12–19. General and Datapath Parameters Parameter Range Description Specifies the protocol that you intend to implement with the Native PHY. The protocol mode selected guides the MegaWizard in identifying legal settings for the 10G PCS datapath.
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Chapter 12: Stratix V Transceiver Native PHY IP Core 10G PCS Parameters 12–21 f For more information refer to the Transmitter FIFO section in Transceiver Architecture in Stratix V Devices. Table 12–20. 10G TX FIFO Parameters (Part 1 of 2) Parameter Range Description Specifies one of the following 3 modes: interlaken phase_comp register TX FIFO Mode ■ interlaken: The TX FIFO acts as an elastic buffer. The FIFO write clock frequency (coreclk) can exceed that of the effective read clock, tx_clkout.
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12–22 Chapter 12: Stratix V Transceiver Native PHY IP Core 10G PCS Parameters Table 12–20. 10G TX FIFO Parameters (Part 2 of 2) Parameter Enable tx_10g_fifo_del port (10GBASE-R) Enable tx_10g_fifo_insert port (10GBASE-R) Range Description On/Off When you turn this option On, the 10G PCS includes the active high tx_10g_fifo_del port. This signal is asserted when a word is deleted from the TX FIFO. This signal is only used for the 10GBASE-R protocol.
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Chapter 12: Stratix V Transceiver Native PHY IP Core 10G PCS Parameters 12–23 Table 12–21. 10G RX FIFO Parameters (Part 2 of 3) Parameter Enable RX FIFO deskew (interlaken) Enable RX FIFO alignment word deletion (interlaken) Enable RX FIFO control word deletion (interlaken) Range Description On/Off When you turn this option On, the RX FIFO also performs deskew. This option is only available for the Interlaken protocol.
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12–24 Chapter 12: Stratix V Transceiver Native PHY IP Core 10G PCS Parameters Table 12–21. 10G RX FIFO Parameters (Part 3 of 3) Parameter Range Enable rx_10g_fifo_align_clr port (Interlaken) Enable rx_10g_fifo_align_en port (Interlaken) Description On/Off When you turn this option On, the 10G PCS includes the rx_10g_fifo_align_clr input port. When this signal is asserted, the FIFO resets and begins searching for a new alignment pattern. This signal is only available for the Interlaken protocol.
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Chapter 12: Stratix V Transceiver Native PHY IP Core 10G PCS Parameters 12–25 Table 12–22. Interlaken Frame Generator Parameters (Part 2 of 2) Parameter Range Description When you turn this option On, the 10G PCS includes the tx_10g_frame_diag_status 2-bit input port. Enable tx_10g_frame_diag_status port On/Off This port contains the lane Status Message from the framing layer Diagnostic Word, bits[33:32]. This message is inserted into the next Diagnostic Word generated by the frame generation block.
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~~12–26 Chapter 12: Stratix V Transceiver Native PHY IP Core 10G PCS Parameters Table 12–23.~~
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Chapter 12: Stratix V Transceiver Native PHY IP Core 10G PCS Parameters 12–27 Interlaken CRC32 Generator and Checker CRC-32 provides a diagnostic tool on a per-lane basis. You can use CRC-32 to trace interface errors back to an individual lane. The CRC-32 calculation covers the whole metaframe including the Diagnostic Word itself. This CRC code value is stored in the CRC32 field of the Diagnostic Word. Table 12–24 describes the CRC-32 parameters.
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12–28 Chapter 12: Stratix V Transceiver Native PHY IP Core 10G PCS Parameters 64b/66b Encoder and Decoder The 64b/66b encoder and decoder conform to the 10GBASE-R protocol specification as described in IEEE 802.3-2008 Clause-49. The 64b/66b encoder sub-block receives data from the TX FIFO and encodes the 64-bit data and 8-bit control characters to the 66-bit data block required by the 10GBASE-R protocol.
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Chapter 12: Stratix V Transceiver Native PHY IP Core 10G PCS Parameters 12–29 Table 12–27. Scrambler and Descrambler Parameters (Part 2 of 2) Parameter Range Description Enable RX scrambler On/Off When you turn this option On, the RX 10G PCS datapath includes the scrambler function. This option is available for the Interlaken and 10GBASE-R protocols. Enable rx_10g_descram_err port On/Off When you turn this option On, the 10G PCS includes the rx_10g_descram_err port.
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12–30 Chapter 12: Stratix V Transceiver Native PHY IP Core 10G PCS Parameters Table 12–29. Bit Reversal and Polarity Inversion Parameters Parameter Enable RX block synchronizer Enable rx_10g_blk_lock port Enable rx_10g_blk_sh_err port Range Description On/Off When you turn this option On, the 10G PCS includes the RX block synchronizer. This option is available for the Interlaken and 10GBASE-R protocols.
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Chapter 12: Stratix V Transceiver Native PHY IP Core Interfaces 12–31 Table 12–30. Gearbox Parameters (Part 2 of 2) Parameter Enable tx_10g_bitslip port Enable rx_10g_bitslip port Range Description On/Of When you turn this option On, the 10G PCS includes the tx_10g_bitslip input port. The data slips 1 bit for every positive edge of the tx_10g_bitslip input. The maximum shift is -1 bits, so that if the PCS is 64 bits wide, you can shift 0–63 bits.
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~~12–32 Chapter 12: Stratix V Transceiver Native PHY IP Core Common Interface Ports The port descriptions use the following variables to represent parameters: ■ —The number of lanes ■~~
—The number of PLLs ■ —the number of CDR references clocks selected Common Interface Ports Common interface consists of reset, clock signals, serial interface ports, control and status ports, parallel data ports, PMA ports, QPI ports, and reconfig interface ports. Figure 12–5 illustrates these ports.
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Chapter 12: Stratix V Transceiver Native PHY IP Core Common Interface Ports 12–33 Table 12–31. Native PHY Common Interfaces (Part 2 of 3) Name rx_cdr_refclk[-1:0] Direction Input Description Input reference clock for the RX PFD circuit. Resets pll_powerdown[-1:0] Input When asserted, resets the TX PLL. Active high, edge sensitive reset signal. tx_analogreset[-1:0] Input When asserted, resets for TX PMA, TX clock generation block, and serializer. Active high, edge sensitive reset signal.
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12–34 Chapter 12: Stratix V Transceiver Native PHY IP Core Common Interface Ports Table 12–31. Native PHY Common Interfaces (Part 3 of 3) Name tx_pma_txdetectrx tx_pma_rxfound rx_pma_qpipulldn Direction Description Input When asserted, the RX detect block in the TX PMA detects the presence of a receiver at the other end of the channel. After receiving a tx_pma_txdetectrx request, the receiver detect block initiates the detection process. Only for QPI applications.
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Chapter 12: Stratix V Transceiver Native PHY IP Core Standard PCS Interface Ports 12–35 Standard PCS Interface Ports Figure 12–6 illustrates the Standard PCI Interfaces. If you enable both the Standard PCS and 10G PCS your top-level HDL file includes all the interfaces for both. Figure 12–6.
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12–36 Chapter 12: Stratix V Transceiver Native PHY IP Core Standard PCS Interface Ports Table 12–32. Standard PCS Interface Ports (Part 2 of 4) Name Dir Synchronous to tx_std_coreclkin/ rx_std_coreclkin Description Phase Compensation FIFO rx_std_pcfifo_full[-1:0] Output Yes RX phase compensation FIFO full status flag. Valid when the Phase Compensation FIFO is not in register mode. rx_std_pcfifo_empty[-1:0] Output Yes RX phase compensation FIFO status empty flag.
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Chapter 12: Stratix V Transceiver Native PHY IP Core Standard PCS Interface Ports 12–37 Table 12–32. Standard PCS Interface Ports (Part 3 of 4) Name Dir Synchronous to tx_std_coreclkin/ rx_std_coreclkin Description Rate Match FIFO rx_std_rm_fifo_empty [-1:0] Output No Rate match FIFO empty flag. When asserted, the rate match FIFO is empty. You must synchronize this signal. rx_std_rm_fifo_full[-1:0] Output No Rate match FIFO full flag. When asserted the rate match FIFO is full.
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12–38 Chapter 12: Stratix V Transceiver Native PHY IP Core 10G PCS Interface Table 12–32. Standard PCS Interface Ports (Part 4 of 4) Name Dir Synchronous to tx_std_coreclkin/ rx_std_coreclkin Description Miscellaneous tx_std_elecidle[-1:0] rx_std_signaldetect[-1:0] Input Output No When asserted, enables a circuit to detect a downstream receiver. It is used for the PCI Express protocol.
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Chapter 12: Stratix V Transceiver Native PHY IP Core 10G PCS Interface 12–39 Table 12–33 describes the signals available for the 10G PCS datapath. When you enable both the 10G and Standard datapaths, both sets of signals are included in the top-level HDL file for the Native PHY. 1 In Table 12–33, the column labeled “Synchronous to tx_10_coreclkin/rx_10g_coreclkin” refers to cases where the phase compensation FIFO is not in register mode. , Table 12–33.
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12–40 Chapter 12: Stratix V Transceiver Native PHY IP Core 10G PCS Interface Table 12–33. 10G PCS Interface Ports (Part 2 of 8) Name Dir Synchronous to tx_10g_coreclkin/ rx_10g_coreclkin Description Basic mode: 67-bit word width: tx_10g_control[9-1:0] (continued) Input Yes ■ [8:3]: Not used ■ [2]: Inversion Bit - must always be set to 1'b0.
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Chapter 12: Stratix V Transceiver Native PHY IP Core 10G PCS Interface 12–41 Table 12–33. 10G PCS Interface Ports (Part 3 of 8) Name Dir Synchronous to tx_10g_coreclkin/ rx_10g_coreclkin Description RX FIFO RX control signals for the Interlaken, 10GBASE-R, and Basic protocols.
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12–42 Chapter 12: Stratix V Transceiver Native PHY IP Core 10G PCS Interface Table 12–33. 10G PCS Interface Ports (Part 4 of 8) Name Dir Synchronous to tx_10g_coreclkin/ rx_10g_coreclkin Description Basic mode: 67-bit mode with Block Sync: ■ [9]: Active-high synchronous status signal that indicates when Block Lock is achieved.
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Chapter 12: Stratix V Transceiver Native PHY IP Core 10G PCS Interface 12–43 Table 12–33. 10G PCS Interface Ports (Part 5 of 8) Name Dir Synchronous to tx_10g_coreclkin/ rx_10g_coreclkin rx_10g_fifo_pfull[-1:0] Output No RX FIFO partially full flag.Synchronous to rx_10g_clkout. This signal is pulse-stretched; you must use a synchronizer. rx_10g_fifo_empty[-1:0] Output Yes Active high RX FIFO empty flag, rx_10g_fifo_pempty [-1:0] Output Yes Active high.
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12–44 Chapter 12: Stratix V Transceiver Native PHY IP Core 10G PCS Interface Table 12–33. 10G PCS Interface Ports (Part 6 of 8) Name tx_10g_frame[-1:0] Dir Output Synchronous to tx_10g_coreclkin/ rx_10g_coreclkin Description No For the Interlaken protocol, asserted to indicate the beginning of a new metaframe inside the frame generator. This signal is pulse-stretched; you must use a synchronizer.
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Chapter 12: Stratix V Transceiver Native PHY IP Core 10G PCS Interface 12–45 Table 12–33. 10G PCS Interface Ports (Part 7 of 8) Name rx_10g_frame_skip_err [-1:0] rx_10g_frame_diag_err [-1:0] rx_10g_fram_diag_status [2-1:0] Dir Output Output outputs Synchronous to tx_10g_coreclkin/ rx_10g_coreclkin Description For the Interlaken protocol, asserted to indicate a Skip Control Word error was received in a Skip Control Word location within the metaframe.
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12–46 Chapter 12: Stratix V Transceiver Native PHY IP Core SDC Timing Constraints Table 12–33. 10G PCS Interface Ports (Part 8 of 8) Name Dir Synchronous to tx_10g_coreclkin/ rx_10g_coreclkin Description BER rx_10g_highber[-1:0] rx_10g_clr_highber_cnt [-1:0] Output Input No For the 10GBASE-R protocol, status signal asserted to indicate a bit error ratio of >10–4. A count of 16 in 125us indicates a bit error ratio of >10–4. Once asserted, it remains high for at least 125 s.
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Chapter 12: Stratix V Transceiver Native PHY IP Core Dynamic Reconfiguration ■ 12–47 You can use the set_max_delay constraint on a given path to create a constraint for asynchronous signals that do not have a specific clock relationship but require a maximum path delay. Example 12–2 illustrates this approach. Example 12–2.
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12–48 Chapter 12: Stratix V Transceiver Native PHY IP Core Simulation Support Assignment Editor. In this example, the pma_bonding_master was originally assigned to physical channel 1. (The original assignment could also have been to physical channel 4.) The to parameter reassigns the pma_bonding_master to the Deterministic Latency PHY instance name. You must substitute the instance name from your design for the instance name shown in quotation marks Example 12–5.
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13. Arria V Transceiver Native PHY IP Core The Arria V Transceiver Native PHY IP Core provides direct access to all control and status signals of the transceiver channels. Unlike other PHY IP Cores, the Native PHY IP Core does not include an Avalon Memory-Mapped (Avalon-MM) interface. Instead, it exposes all signals directly as ports.
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13–2 Chapter 13: Arria V Transceiver Native PHY IP Core Device Family Support In a typical design, the separately instantiated Transceiver PHY Reset Controller drives reset signals to Native PHY and receives calibration and locked status signal from the Native PHY. The Native PHY reconfiguration buses connect the external Transceiver Reconfiguration Controller for calibration and dynamic reconfiguration of the channel and PLLs. You specify the initial configuration when you parameterize the IP core.
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Chapter 13: Arria V Transceiver Native PHY IP Core General Parameters 13–3 General Parameters Table 13–2 lists the parameters available on the General Options tab. Table 13–2. General and Datapath Options Name Device speed grade Range Description 3fastest–6_H6 Specifies the speed grade. Allows you to specify the message level, as follows: Message level for rule violations ■ error: Quartus II checker will not create an instance with invalid parameters.
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13–4 Chapter 13: Arria V Transceiver Native PHY IP Core PMA Parameters PMA Parameters Table 13–3 describes the options available for the PMA. f For more information about the PMA, refer to the PMA Architecture section in the Transceiver Architecture in Arria V Devices.Some parameters have ranges where the value is specified as Device Dependent. For such parameters, the possible range of frequencies and bandwidths depends on the device, speed grade, and other design characteristics.
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Chapter 13: Arria V Transceiver Native PHY IP Core PMA Parameters 13–5 Table 13–4. TX PMA Parameters Parameter Range Description Number of TX PLLs 1–4 Specifies the number of TX PLLs required. More than 1 PLL is typically required if your design reconfigures channels to run at multiple frequencies. Main TX PLL logical index 0–3 Specifies the index of the TX PLL used in the initial configuration.
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13–6 Chapter 13: Arria V Transceiver Native PHY IP Core PMA Parameters RX PMA Parameters Table 13–6 describes the RX PMA options you can specify. f For more information about the CDR circuitry, refer to the Receiver PMA Datapath section in the Transceiver Architecture in Arria V Devices. Table 13–6. RX PMA Parameters Parameter Range Enable CDR dynamic reconfiguration On/Off Description When you turn this option On, you can dynamically change the data rate of the CDR circuit.
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Chapter 13: Arria V Transceiver Native PHY IP Core PMA Parameters 13–7 Table 13–8 lists the best- case latency for the LSB of the TX serializer for all supported interface widths for the PMA Direct datapath. Table 13–8. Latency for TX Serialization n Arria V Devices FPGA Fabric Interface Width Arria V Latency in UI 8 bits 43 10 bits 53 16 bits 67 20 bits 83 64 bits 131 80 bits 163 Table 13–9 shows the bits used for all FPGA fabric to PMA interface widths.
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13–8 Chapter 13: Arria V Transceiver Native PHY IP Core Standard PCS Parameters Standard PCS Parameters Figure 13–2 shows the complete datapath and clocking for the Standard PCS. You use parameters available in the GUI to enable or disable the individual blocks in the Standard PCS. Figure 13–2.
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Chapter 13: Arria V Transceiver Native PHY IP Core Standard PCS Parameters 13–9 Table 13–10. General and Datapath Parameters (Part 2 of 2) Parameter Range Description Standard PCS/PMA interface width 8, 10,16, 20 Specifies the width of the datapath that connects the FPGA fabric to the PMA. The transceiver interface width depends upon whether you enable 8B/10B. To simplify connectivity between the FPGA fabric and PMA, the bus bits used are not contiguous for 16- and 32-bit buses.
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13–10 Chapter 13: Arria V Transceiver Native PHY IP Core Standard PCS Parameters Table 13–11. Phase Compensation FIFO Parameters Parameter Range Description Enable rx_std_pcfifo_empty port On/Off When you turn this option On, the RX Phase compensation FIFO outputs a FIFO empty status flag. Enable rx_std_rmfifo_empty port On/Off When you turn this option On, the rate match FIFO outputs a FIFO empty status flag.
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Chapter 13: Arria V Transceiver Native PHY IP Core Standard PCS Parameters 13–11 Table 13–12. Byte Ordering Block Parameters (Part 2 of 2) Parameter Range Description Specifies the pad pattern that is inserted by the byte ordering block. This value is inserted when the byte order pattern is recognized.
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13–12 Chapter 13: Arria V Transceiver Native PHY IP Core Standard PCS Parameters 8B/10B The 8B/10B encoder generates 10-bit code groups from the 8-bit data and 1-bit control identifier. In 8-bit width mode, the 8B/10B encoder translates the 8-bit data to a 10-bit code group (control word or data word) with proper disparity. The 8B/10B decoder decodes the data into an 8-bit data and 1-bit control identifier. Table 13–14 describes the 8B/10B encoder and decoder options.
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Chapter 13: Arria V Transceiver Native PHY IP Core Standard PCS Parameters 13–13 f For more information refer to the Word Aligner section in the Transceiver Architecture in Arria V Devices. Table 13–16. Word Aligner and Bit-Slip Parameters Parameter Range Description Enable TX bit-slip On/Off When you turn this option On, the PCS includes the bit-slip function. The outgoing TX data can be slipped by the number of bits specified by the tx_bitslipboundarysel control signal.
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13–14 Chapter 13: Arria V Transceiver Native PHY IP Core Standard PCS Parameters Bit Reversal and Polarity Inversion These functions allow you to reverse bit order, byte order, and polarity to correct errors and to accommodate different layouts of data. Table 13–17 describes these parameters. Table 13–17.
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Chapter 13: Arria V Transceiver Native PHY IP Core Interfaces 13–15 Interfaces The Native PHY includes several interfaces that are common to all parameterizations. The Native PHY allows you to enable ports, even for disabled blocks to facilitate dynamic reconfiguration.
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13–16 Chapter 13: Arria V Transceiver Native PHY IP Core Common Interface Ports Table 13–18. Native PHY Common Interfaces (Part 1 of 2) Name Direction Description Clock Inputs and Output Signals tx_pll_refclk[-1:0] Input tx_pma_clkout[-1:0] Output TX parallel clock output from PMA. This clock is only available in PMA direct mode.
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Chapter 13: Arria V Transceiver Native PHY IP Core Common Interface Ports 13–17 Table 13–18. Native PHY Common Interfaces (Part 2 of 2) Name rx_set_locktodata[-1:0] rx_set_locktoref[-1:0] Direction Description Input When asserted, programs the RX CDR to manual lock to data mode in which you control the reset sequence using the rx_set_locktoref and rx_set_locktodata.
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~~13–18 Chapter 13: Arria V Transceiver Native PHY IP Core Standard PCS Interface Ports Standard PCS Interface Ports Figure 13–4 illustrates the Standard PCS interfaces. Figure 13–4.~~
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Chapter 13: Arria V Transceiver Native PHY IP Core Standard PCS Interface Ports 13–19 Table 13–19. Standard PCS Interface Ports (Part 2 of 3) Dir Synchronou s to tx_std_core clkin/ rx_std_core clkin tx_std_pcfifo_full [-1:0] Output Yes TX phase compensation FIFO status full flag. tx_std_pcfifo_empty [-1:0] Output Yes TX phase compensation FIFO status empty flag.
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13–20 Chapter 13: Arria V Transceiver Native PHY IP Core SDC Timing Constraints Table 13–19. Standard PCS Interface Ports (Part 3 of 3) Name Dir Synchronou s to tx_std_core clkin/ rx_std_core clkin tx_std_bitslipboundarysel [5-1:0] Input No Bit-Slip boundary selection signal. Specifies the number of bits that the TX bit slipper must slip. rx_std_bitslipboundarysel [5-1:0] Output No This signal operates when the word aligner is in bit-slip word alignment mode.
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Chapter 13: Arria V Transceiver Native PHY IP Core SDC Timing Constraints ■ 13–21 You can cut these paths in your Synopsys Design Constraints (.sdc) file by using the set_false_path command as shown in Example 13–1. Example 13–1.
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13–22 Chapter 13: Arria V Transceiver Native PHY IP Core Dynamic Reconfiguration Dynamic Reconfiguration As silicon progresses towards smaller process nodes, circuit performance is affected more by variations due to process, voltage, and temperature (PVT). These process variations result in analog voltages that can be offset from required ranges. The calibration performed by the dynamic reconfiguration interface compensates for variations due to PVT.
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14. Arria V GZ Transceiver Native PHY IP Core The Arria V GZTransceiver Native PHY IP Core provides direct access to all control and status signals of the transceiver channels. Unlike other PHY IP Cores, the Native PHY IP Core does not include an Avalon Memory-Mapped (Avalon-MM) interface. Instead, it exposes all signals directly as ports.
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14–2 Chapter 14: Arria V GZ Transceiver Native PHY IP Core Device Family Support Figure 14–1 illustrates the use of the Arria V GZ Transceiver Native PHY IP Core. As this figure illustrates, TX PLL and clock data recovery (CDR) reference clocks from the pins of the device are input to the PLL module and CDR logic. When enabled, the 10G or Standard PCS drives TX parallel data and receives RX parallel data. When neither PCS is enabled the Native PHY operates in PMA Direct mode. Figure 14–1.
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Chapter 14: Arria V GZ Transceiver Native PHY IP Core Performance and Resource Utilization 14–3 Table 14–1 shows the level of support offered by the Arria V GZ Transceiver Native PHY IP Core for Altera device families. Table 14–1.
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14–4 Chapter 14: Arria V GZ Transceiver Native PHY IP Core Parameterizing the Arria V GZ Native PHY Parameterizing the Arria V GZ Native PHY Complete the following steps to configure the Arria V GZ Native PHY IP Core in the MegaWizard Plug-In Manager: 1. For Which device family will you be using? select Arria V GZ from the list. 2. Click Installed Plug-Ins > Interfaces > Transceiver PHY > Arria V GZ Native PHY v12.1. 3.
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Chapter 14: Arria V GZ Transceiver Native PHY IP Core PMA Parameters 14–5 Table 14–2. General and Datapath Options (Part 2 of 2) Name Range Description In Non–bonded mode, each channel is paired with a PLL. During Quartus II compilation, the Fitter merges all PLLs that meet merging requirements into a single PLL. Non–bonded Bonding mode ×6 fb_compensation Select ×6 to use the same clock source for up to 6 channels in a single transceiver bank, resulting in reduced clock skew.
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14–6 Chapter 14: Arria V GZ Transceiver Native PHY IP Core PMA Parameters Table 14–3. PMA Options (Part 2 of 2) Parameter TX PLL base data rate Range Description Device Dependent Specifies the base data rate for the clock input to the TX PLL. Select a base data rate that minimizes the number of PLLs required to generate all the clocks required for data transmission. By selecting an appropriate base data rate, you can change data rates by changing the divider used by the clock generation block.
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Chapter 14: Arria V GZ Transceiver Native PHY IP Core PMA Parameters 14–7 TX PLL Table 14–5 allows you to define multiple TX PLLs for your Native PHY. The Native PHY GUI provides a separate tab for each TXPLL. Table 14–5. TX PLL Parameters Parameter PLL type Range CMU, ATX Description The CMU PLL is available for Arria V devices.You can select either the CMU or ATX PLL. the CMU PLL has a larger frequency range than the ATX PLL.
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14–8 Chapter 14: Arria V GZ Transceiver Native PHY IP Core PMA Parameters RX PMA Parameters Table 14–6 describes the RX PMA options you can specify. f For more information about the CDR circuitry, refer to the Receiver PMA Datapath section in the Transceiver Architecture in Arria V Devices. Table 14–6. RX PMA Parameters Parameter Enable CDR dynamic reconfiguration Range Description On/Off When you turn this option On, you can dynamically change the reference clock input the CDR circuit.
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Chapter 14: Arria V GZ Transceiver Native PHY IP Core PMA Parameters 14–9 Table 14–7. Latency for RX Deserialization in Arria V GZ Devices (Part 2 of 2) FPGA Fabric Interface Width Arria V GZ Latency in UI 40 bits 43 64 bits 99 80 bits 123 Table 14–8 lists the best case latency for the most significant bit of a word for the RX deserializer. For example, for an 8-bit interface width, the latencies in UI are 11 for bit 7, 12 for bit 6, 13 for bit 5, and so on. Table 14–8.
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14–10 Chapter 14: Arria V GZ Transceiver Native PHY IP Core PMA Parameters Table 14–11 shows the bits used for all FPGA fabric to PMA interface widths. Regardless of the FPGA Fabric Interface Width selected, all 80 bits are exposed for the TX and RX parallel data ports. However, depending upon the interface width selected not all bits on the bus will be active. Table 14–11 shows which bits are active for each FPGA Fabric Interface Width selection.
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Chapter 14: Arria V GZ Transceiver Native PHY IP Core Standard PCS Parameters 14–11 Standard PCS Parameters Figure 14–3 shows the complete datapath and clocking for the Standard PCS. You use parameters available in the GUI to enable or disable the individual blocks in the Standard PCS. Figure 14–3.
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14–12 Chapter 14: Arria V GZ Transceiver Native PHY IP Core Standard PCS Parameters Table 14–12 describes the general and datapath options for the Standard PCS. Table 14–12. General and Datapath Parameters Parameter Range Description Specifies the protocol that you intend to implement with the Native PHY. The protocol mode selected guides the MegaWizard in identifying legal settings for the Standard PCS datapath.
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Chapter 14: Arria V GZ Transceiver Native PHY IP Core Standard PCS Parameters 14–13 Phase Compensation FIFO The phase compensation FIFO assures clean data transfer to and from the FPGA fabric by compensating for the clock phase difference between the low-speed parallel clock and FPGA fabric interface clock. Table 14–13 describes the options for the phase compensation FIFO. Table 14–13.
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14–14 Chapter 14: Arria V GZ Transceiver Native PHY IP Core Standard PCS Parameters f For more information refer to the Byte Ordering section in the Transceiver Architecture in Arria V Devices. Table 14–14. Byte Ordering Block Parameters Parameter Enable RX byte ordering Range Description On/Off When you turn this option On, the PCS includes the byte ordering block. Specifies the control mode for the byte ordering block.
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Chapter 14: Arria V GZ Transceiver Native PHY IP Core Standard PCS Parameters 14–15 Byte Serializer and Deserializer The byte serializer and deserializer allow the PCS to operate at twice the data width of the PMA serializer. This feature allows the PCS to run at a lower frequency and accommodate a wider range of FPGA interface widths. Table 14–15 describes the byte serialization and deserialization options you can specify.
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14–16 Chapter 14: Arria V GZ Transceiver Native PHY IP Core Standard PCS Parameters f Table 14–17. Rate Match FIFO Parameters Parameter Range Description On/Off When you turn this option On, the PCS includes a FIFO to compensate for the very small frequency differences between the local system clock and the RX recovered clock. RX rate match insert/delete +ve pattern (hex) User-specified 20 bit pattern Specifies the +ve (positive) disparity value for the RX rate match FIFO as a hexadecimal string.
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Chapter 14: Arria V GZ Transceiver Native PHY IP Core Standard PCS Parameters 14–17 Table 14–18. Word Aligner and Bit-Slip Parameters (Part 2 of 2) Parameter Range RX word aligner pattern length 7,8,10,16,20,32 RX word aligner pattern (hex) User-specified Description Specifies the length of the pattern the word aligner uses for alignment. Specifies the word aligner pattern in hex.
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14–18 Chapter 14: Arria V GZ Transceiver Native PHY IP Core Standard PCS Parameters Table 14–19. Bit Reversal and Polarity Inversion Parameters (Part 2 of 2) Parameter Range Description Enable TX polarity inversion On/Off When you turn this option On, the tx_std_polinv port controls polarity inversion of TX parallel data before transmitting the parallel data to the PMA.
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Chapter 14: Arria V GZ Transceiver Native PHY IP Core 10G PCS Parameters 14–19 10G PCS Parameters Figure 14–4 shows the complete datapath and clocking for the 10G PCS. You use parameters available in the GUI to enable or disable the individual blocks in the 10G PCS. Figure 14–4.
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14–20 Chapter 14: Arria V GZ Transceiver Native PHY IP Core 10G PCS Parameters Table 14–20 describes the general and datapath options for the 10G PCS. Table 14–20. General and Datapath Parameters Parameter Range Description Specifies the protocol that you intend to implement with the Native PHY. The protocol mode selected guides the MegaWizard in identifying legal settings for the 10G PCS datapath.
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Chapter 14: Arria V GZ Transceiver Native PHY IP Core 10G PCS Parameters 14–21 f Table 14–21. 10G TX FIFO Parameters Parameter Range Description Specifies one of the following 3 modes: interlaken phase_comp register TX FIFO Mode ■ interlaken: The TX FIFO acts as an elastic buffer. The FIFO write clock frequency (coreclk) can exceed that of the effective read clock, tx_clkout. You can control writes to the FIFO with tx_data_valid.
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14–22 Chapter 14: Arria V GZ Transceiver Native PHY IP Core 10G PCS Parameters 10G RX FIFO The RX FIFO is the interface between RX data from the FPGA fabric and the PCS. This FIFO is an asynchronous 73-bit wide, 32-deep memory buffer It also provides full, empty, partially full, and empty flags based on programmable thresholds. Table 14–22 describes the 10G RX FIFO parameters. f Table 14–22.
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Chapter 14: Arria V GZ Transceiver Native PHY IP Core 10G PCS Parameters 14–23 Table 14–22. 10G RX FIFO Parameters (Part 2 of 2) Parameter Range Description When you turn this option On, the 10G PCS includes the rx_data_valid signal which Indicates when rx_data is valid.
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14–24 Chapter 14: Arria V GZ Transceiver Native PHY IP Core 10G PCS Parameters Interlaken Frame Generator TX Frame generator generates the metaframe. It encapsulates the payload from MAC with the framing layer control words, including sync, scrambler, skip and diagnostic words. Table 14–23 describes the Interlaken frame generator parameters. f Table 14–23.
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Chapter 14: Arria V GZ Transceiver Native PHY IP Core 10G PCS Parameters 14–25 f Table 14–24. Interlaken Frame Synchronizer Parameters Parameter Range Description teng_tx_framsync_enable On/Off When you turn this option On, the 10G PCS frame generator is enabled. Enable rx_10g_frame port On/Off When you turn this option On, the 10G PCS includes the rx_10g_frame output port. This signal is asserted to indicate the beginning of a new metaframe inside.
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14–26 Chapter 14: Arria V GZ Transceiver Native PHY IP Core 10G PCS Parameters Interlaken CRC32 Generator and Checker CRC-32 provides a diagnostic tool on a per-lane basis. You can use CRC-32 to trace interface errors back to an individual lane. The CRC-32 calculation covers the whole metaframe including the Diagnostic Word itself. This CRC code value is stored in the CRC32 field of the Diagnostic Word. Table 14–25 describes the CRC-32 parameters. f Table 14–25.
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Chapter 14: Arria V GZ Transceiver Native PHY IP Core 10G PCS Parameters 14–27 64b/66b Encoder and Decoder The 64b/66b encoder and decoder conform to the 10GBASE-R protocol specification as described in IEEE 802.3-2008 Clause-49. The 64b/66b encoder sub-block receives data from the TX FIFO and encodes the 64-bit data and 8-bit control characters to the 66-bit data block required by the 10GBASE-R protocol.
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14–28 Chapter 14: Arria V GZ Transceiver Native PHY IP Core 10G PCS Parameters Interlaken Disparity Generator and Checker The Disparity Generator monitors the data transmitted to ensure that the running disparity remains within a 96-bit bound. It adds the 67th bit to indicate whether or not the data is inverted. The Disparity Checker monitors the status of the 67th bit of the incoming word to determine whether or not to invert bits[63:0] of the received word.
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Chapter 14: Arria V GZ Transceiver Native PHY IP Core Interfaces 14–29 Gearbox The gearbox adapts the PMA data width to a wider PCS data width when the PCS is not two or four times the PMA width.Table 14–31 describes the gearbox parameters. Table 14–31. Gearbox Parameters Parameter Range Description Enable TX data polarity inversion On/Off When you turn this option On, the gearbox inverts the polarity of TX data allowing you to correct incorrect placement and routing on the PCB.
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~~14–30 Chapter 14: Arria V GZ Transceiver Native PHY IP Core Common Interface Ports The port descriptions use the following variables to represent parameters: ■ —The number of lanes ■~~
—The number of PLLs ■ —the number of CDR references clocks selected Common Interface Ports Common interface consists of reset, clock signals, serial interface ports, control and status ports, parallel data ports, PMA ports, QPI ports, and reconfig interface ports. Figure 14–5 illustrates these ports.
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Chapter 14: Arria V GZ Transceiver Native PHY IP Core Common Interface Ports 14–31 Table 14–32. Native PHY Common Interfaces (Part 2 of 3) Name rx_cdr_refclk[-1:0] Direction Input Description Input reference clock for the RX PFD circuit. Resets pll_powerdown[-1:0] Input When asserted, resets the TX PLL. Active high, edge sensitive reset signal. tx_analogreset[-1:0] Input When asserted, resets for TX PMA, TX clock generation block, and serializer. Active high, edge sensitive reset signal.
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14–32 Chapter 14: Arria V GZ Transceiver Native PHY IP Core Common Interface Ports Table 14–32. Native PHY Common Interfaces (Part 3 of 3) Name tx_pma_txdetectrx tx_pma_rxfound rx_pma_qpipulldn Direction Description Input When asserted, the RX detect block in the TX PMA detects the presence of a receiver at the other end of the channel. After receiving a tx_pma_txdetectrx request, the receiver detect block initiates the detection process. Only for QPI applications.
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Chapter 14: Arria V GZ Transceiver Native PHY IP Core Standard PCS Interface Ports 14–33 Standard PCS Interface Ports Figure 14–6 illustrates the Standard PCI Interfaces. If you enable both the Standard PCS and 10G PCS your top-level HDL file includes all the interfaces for both. Figure 14–6.
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14–34 Chapter 14: Arria V GZ Transceiver Native PHY IP Core Standard PCS Interface Ports Table 14–33. Standard PCS Interface Ports (Part 2 of 4) Name Dir Synchronous to tx_std_coreclkin/ rx_std_coreclkin Description Phase Compensation FIFO rx_std_pcfifo_full[-1:0] Output Yes RX phase compensation FIFO full status flag. Valid when the Phase Compensation FIFO is not in register mode. rx_std_pcfifo_empty[-1:0] Output Yes RX phase compensation FIFO status empty flag.
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Chapter 14: Arria V GZ Transceiver Native PHY IP Core Standard PCS Interface Ports 14–35 Table 14–33. Standard PCS Interface Ports (Part 3 of 4) Name Dir Synchronous to tx_std_coreclkin/ rx_std_coreclkin Description Rate Match FIFO rx_std_rm_fifo_empty [-1:0] Output No Rate match FIFO empty flag. When asserted, the rate match FIFO is empty. You must synchronize this signal. rx_std_rm_fifo_full[-1:0] Output No Rate match FIFO full flag. When asserted the rate match FIFO is full.
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14–36 Chapter 14: Arria V GZ Transceiver Native PHY IP Core 10G PCS Interface Table 14–33. Standard PCS Interface Ports (Part 4 of 4) Name Dir Synchronous to tx_std_coreclkin/ rx_std_coreclkin Description Miscellaneous tx_std_elecidle[-1:0] rx_std_signaldetect[-1:0] Input Output No When asserted, enables a circuit to detect a downstream receiver. It is used for the PCI Express protocol.
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Chapter 14: Arria V GZ Transceiver Native PHY IP Core 10G PCS Interface 14–37 Table 14–34 describes the signals available for the 10G PCS datapath. When you enable both the 10G and Standard datapaths, both sets of signals are included in the top-level HDL file for the Native PHY. 1 In Table 14–34, the column labeled “Synchronous to tx_10_coreclkin/rx_10g_coreclkin” refers to cases where the phase compensation FIFO is not in register mode. , Table 14–34.
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14–38 Chapter 14: Arria V GZ Transceiver Native PHY IP Core 10G PCS Interface Table 14–34. 10G PCS Interface Ports (Part 2 of 8) Name Dir Synchronous to tx_10g_coreclkin/ rx_10g_coreclkin Description Basic mode: 67-bit word width: tx_10g_control[9-1:0] (continued) Input Yes ■ [8:3]: Not used ■ [2]: Inversion Bit - must always be set to 1'b0.
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Chapter 14: Arria V GZ Transceiver Native PHY IP Core 10G PCS Interface 14–39 Table 14–34. 10G PCS Interface Ports (Part 3 of 8) Name Dir Synchronous to tx_10g_coreclkin/ rx_10g_coreclkin Description RX FIFO RX control signals for the Interlaken, 10GBASE-R, and Basic protocols.
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14–40 Chapter 14: Arria V GZ Transceiver Native PHY IP Core 10G PCS Interface Table 14–34. 10G PCS Interface Ports (Part 4 of 8) Name Dir Synchronous to tx_10g_coreclkin/ rx_10g_coreclkin Description Basic mode: 67-bit mode with Block Sync: ■ [9]: Active-high synchronous status signal that indicates when Block Lock is achieved.
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Chapter 14: Arria V GZ Transceiver Native PHY IP Core 10G PCS Interface 14–41 Table 14–34. 10G PCS Interface Ports (Part 5 of 8) Name Dir Synchronous to tx_10g_coreclkin/ rx_10g_coreclkin rx_10g_fifo_pfull[-1:0] Output No RX FIFO partially full flag.Synchronous to rx_10g_clkout. This signal is pulse-stretched; you must use a synchronizer. rx_10g_fifo_empty[-1:0] Output Yes Active high RX FIFO empty flag, rx_10g_fifo_pempty [-1:0] Output Yes Active high.
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14–42 Chapter 14: Arria V GZ Transceiver Native PHY IP Core 10G PCS Interface Table 14–34. 10G PCS Interface Ports (Part 6 of 8) Name tx_10g_frame[-1:0] Dir Output Synchronous to tx_10g_coreclkin/ rx_10g_coreclkin Description No For the Interlaken protocol, asserted to indicate the beginning of a new metaframe inside the frame generator. This signal is pulse-stretched; you must use a synchronizer.
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Chapter 14: Arria V GZ Transceiver Native PHY IP Core 10G PCS Interface 14–43 Table 14–34. 10G PCS Interface Ports (Part 7 of 8) Name rx_10g_frame_skip_err [-1:0] rx_10g_frame_diag_err [-1:0] rx_10g_fram_diag_status [2-1:0] Dir Output Output outputs Synchronous to tx_10g_coreclkin/ rx_10g_coreclkin Description For the Interlaken protocol, asserted to indicate a Skip Control Word error was received in a Skip Control Word location within the metaframe.
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14–44 Chapter 14: Arria V GZ Transceiver Native PHY IP Core SDC Timing Constraints Table 14–34. 10G PCS Interface Ports (Part 8 of 8) Name Dir Synchronous to tx_10g_coreclkin/ rx_10g_coreclkin Description BER rx_10g_highber[-1:0] rx_10g_clr_highber_cnt [-1:0] Output Input No For the 10GBASE-R protocol, status signal asserted to indicate a bit error ratio of >10–4. A count of 16 in 125us indicates a bit error ratio of >10–4. Once asserted, it remains high for at least 125 s.
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Chapter 14: Arria V GZ Transceiver Native PHY IP Core Dynamic Reconfiguration ■ 14–45 You can use the set_max_delay constraint on a given path to create a constraint for asynchronous signals that do not have a specific clock relationship but require a maximum path delay. Example 14–2 illustrates this approach. Example 14–2.
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14–46 Chapter 14: Arria V GZ Transceiver Native PHY IP Core Simulation Support Assignment Editor. In this example, the pma_bonding_master was originally assigned to physical channel 1. (The original assignment could also have been to physical channel 4.) The to parameter reassigns the pma_bonding_master to the Deterministic Latency PHY instance name. You must substitute the instance name from your design for the instance name shown in quotation marks Example 14–5.
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15. Cyclone V Transceiver Native PHY IP Core The Cyclone V Transceiver Native PHY IP Core provides direct access to all control and status signals of the transceiver channels. Unlike other PHY IP Cores, the Native PHY IP Core does not include an Avalon Memory-Mapped (Avalon-MM) interface. Instead, it exposes all signals directly as ports. The Cyclone V Transceiver Native PHY IP Core includes the Standard PCS. You can select the PCS functions and control and status port that your transceiver PHY requires.
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15–2 Chapter 15: Cyclone V Transceiver Native PHY IP Core Device Family Support Device Family Support IP cores provide either final or preliminary support for target Altera device families. These terms have the following definitions: ■ Final support—Verified with final timing models for this device. ■ Preliminary support—Verified with preliminary timing models for this device. Table 15–1 shows the level of support offered by the Cyclone V Transceiver Native PHY IP Core for Altera device families.
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Chapter 15: Cyclone V Transceiver Native PHY IP Core General Parameters 15–3 General Parameters Table 15–2 lists the parameters available on the General Options tab. Table 15–2. General and Datapath Options Name Range Device speed grade fastest Description Specifies the speed grade. Allows you to specify the message level, as follows: Message level for rule violations ■ error: Quartus II checker will not create an instance with invalid parameters.
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15–4 Chapter 15: Cyclone V Transceiver Native PHY IP Core PMA Parameters PMA Parameters Table 15–3 describes the options available for the PMA. f For more information about the PMA, refer to the PMA Architecture section in the Transceiver Architecture in Cyclone V Devices.Some parameters have ranges where the value is specified as Device Dependent. For such parameters, the possible range of frequencies and bandwidths depends on the device, speed grade, and other design characteristics.
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Chapter 15: Cyclone V Transceiver Native PHY IP Core PMA Parameters 15–5 Table 15–4. TX PMA Parameters Parameter Range Description Number of TX PLLs 1–4 Specifies the number of TX PLLs required. More than 1 PLL is typically required if your design reconfigures channels to run at multiple frequencies. Main TX PLL logical index 0–3 Specifies the index of the TX PLL used in the initial configuration.
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15–6 Chapter 15: Cyclone V Transceiver Native PHY IP Core PMA Parameters RX PMA Parameters Table 15–6 describes the RX PMA options you can specify. f For more information about the CDR circuitry, refer to the Receiver PMA Datapath section in the Transceiver Architecture in Cyclone V Devices. Table 15–6. RX PMA Parameters Parameter Range Enable CDR dynamic reconfiguration On/Off Description When you turn this option On, you can dynamically change the data rate of the CDR circuit.
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Chapter 15: Cyclone V Transceiver Native PHY IP Core PMA Parameters 15–7 Table 15–8 lists the best- case latency for the LSB of the TX serializer for all supported interface widths for the PMA Direct datapath. Table 15–8. Latency for TX Serialization in Cyclone V Devices FPGA Fabric Interface Width Arria V Latency in UI 8 bits 43 10 bits 53 16 bits 67 20 bits 83 64 bits 131 80 bits 163 Table 15–9 shows the bits used for all FPGA fabric to PMA interface widths.
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15–8 Chapter 15: Cyclone V Transceiver Native PHY IP Core Standard PCS Parameters Standard PCS Parameters Figure 15–3 shows the complete datapath and clocking for the Standard PCS. You use parameters available in the GUI to enable or disable the individual blocks in the Standard PCS. Figure 15–2.
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Chapter 15: Cyclone V Transceiver Native PHY IP Core Standard PCS Parameters 15–9 Table 15–10 describes the general and datapath options for the Standard PCS. Table 15–10. General and Datapath Parameters Parameter Range Description Specifies the protocol that you intend to implement with the Native PHY. The protocol mode selected guides the MegaWizard in identifying legal settings for the Standard PCS datapath.
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15–10 Chapter 15: Cyclone V Transceiver Native PHY IP Core Standard PCS Parameters f For more information refer to the Receiver Phase Compensation FIFO and Transmitter Phase Compensation FIFO sections in Transceiver Architecture in Cyclone V Devices. Table 15–11. Phase Compensation FIFO Parameters Parameter Range Description The following 2 modes are possible: TX FIFO mode low_latency register_fifo ■ low_latency: This mode adds 3–4 cycles of latency to the TX datapath.
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Chapter 15: Cyclone V Transceiver Native PHY IP Core Standard PCS Parameters 15–11 Byte Ordering Block Parameters The RX byte ordering block realigns the data coming from the byte deserializer. This block is necessary when the PCS to FPGA fabric interface width is greater than the PCS datapath. Because the timing of the RX PCS reset logic is indeterminate, the byte ordering at the output of the byte deserializer may or may not match the original byte ordering of the transmitted data.
~~PAGE 366~~
15–12 Chapter 15: Cyclone V Transceiver Native PHY IP Core Standard PCS Parameters Table 15–12. Byte Ordering Block Parameters (Part 2 of 2) Parameter Range Enable rx_std_byteorder_ena port Enable rx_std_byteorder_flag port Description On/Off Enables the optional rx_std_byte_order_ena control input port. When this signal is asserted, the byte ordering block initiates a byte ordering operation if the Byte ordering control mode is set to manual.
~~PAGE 367~~
Chapter 15: Cyclone V Transceiver Native PHY IP Core Standard PCS Parameters 15–13 f For more information refer to the 8B/10B Decoder in Single-Width Mode, 8B/10B Decoder in Double-Width Mode and 8B/10B Decoder sections in Transceiver Architecture in Cyclone V Devices. Table 15–14. 8B/10B Encoder and Decoder Parameters Parameter Range Description On/Off When you turn this option On, the PCS includes the 8B/10B encoder.
~~PAGE 368~~
15–14 Chapter 15: Cyclone V Transceiver Native PHY IP Core Standard PCS Parameters f For more information refer to the Word Aligner section in Transceiver Architecture in Cyclone V Devices. Table 15–16. Word Aligner and Bit-Slip Parameters Parameter Range Description Enable TX bit-slip On/Off When you turn this option On, the PCS includes the bit-slip function. The outgoing TX data can be slipped by the number of bits specified by the tx_bitslipboundarysel control signal.
~~PAGE 369~~
Chapter 15: Cyclone V Transceiver Native PHY IP Core Standard PCS Parameters 15–15 Bit Reversal and Polarity Inversion These functions allow you to reverse bit order, byte order, and polarity to correct errors and to accommodate different layouts of data. Table 15–17 describes these parameters. Table 15–17.
~~PAGE 370~~
15–16 Chapter 15: Cyclone V Transceiver Native PHY IP Core Interfaces Interfaces The Native PHY includes several interfaces that are common to all parameterizations. The Native PHY allows you to enable ports, even for disabled blocks to facilitate dynamic reconfiguration.
~~PAGE 371~~
Chapter 15: Cyclone V Transceiver Native PHY IP Core Common Interface Ports 15–17 Table 15–18. Native PHY Common Interfaces (Part 2 of 3) Name Direction Description tx_pll_refclk[-1:0] Input rx_pma_clkout[-1:0] Output RX parallel clock (recovered clock) output from PMA rx_clklow[-1:0] Output The RX parallel recovered clock input to the phase frequency detector (PFD). When operating CDR in manual lock mode, you can use this clock as an input with rx_fref to an external PPM detector.
~~PAGE 372~~
15–18 Chapter 15: Cyclone V Transceiver Native PHY IP Core Standard PCS Interface Ports Table 15–18. Native PHY Common Interfaces (Part 3 of 3) Name rx_set_locktoref[-1:0] Direction Description Input When asserted, programs the RX CDR to manual lock to reference mode in which you control the reset sequence using the rx_set_locktoref and rx_set_locktodata.
~~PAGE 373~~
Chapter 15: Cyclone V Transceiver Native PHY IP Core Standard PCS Interface Ports 15–19 Table 15–19 describes the ports available for the Standard PCS interface. Table 15–19. Standard PCS Interface Ports (Part 1 of 3) Name Dir Synchronou s to tx_std_core clkin/ rx_std_core clkin Description Clocks tx_std_clkout[-1:0] Output — TX Parallel clock output as shown in The Standard PCS Datapath figure.
~~PAGE 374~~
15–20 Chapter 15: Cyclone V Transceiver Native PHY IP Core Standard PCS Interface Ports Table 15–19. Standard PCS Interface Ports (Part 2 of 3) Name Dir Synchronou s to tx_std_core clkin/ rx_std_core clkin Description 8B/10B rx_std_polinv[-1:0] Input No Polarity inversion for the 8B/10B decoder, When set, the RX channels invert the polarity of the received data.
~~PAGE 375~~
Chapter 15: Cyclone V Transceiver Native PHY IP Core SDC Timing Constraints 15–21 Table 15–19. Standard PCS Interface Ports (Part 3 of 3) Name Dir rx_std_bitslip[-1:0] Input Synchronou s to tx_std_core clkin/ rx_std_core clkin Description No Used when word aligner mode is bit-slip mode. For every rising edge of the rx_std_bitslip signal, the word boundary is shifted by 1 bit. Each bitslip removes the earliest received bit from the received data. You must synchronize this signal.
~~PAGE 376~~
15–22 Chapter 15: Cyclone V Transceiver Native PHY IP Core SDC Timing Constraints ■ You can cut these paths in your Synopsys Design Constraints (.sdc) file by using the set_false_path command as shown in Example 15–1. Example 15–1.
~~PAGE 377~~
Chapter 15: Cyclone V Transceiver Native PHY IP Core Dynamic Reconfiguration 15–23 Dynamic Reconfiguration As silicon progresses towards smaller process nodes, circuit performance is affected more by variations due to process, voltage, and temperature (PVT). These process variations result in analog voltages that can be offset from required ranges. The calibration performed by the dynamic reconfiguration interface compensates for variations due to PVT.
~~PAGE 378~~
~~15–24 Altera Transceiver PHY IP Core User Guide Chapter 15: Cyclone V Transceiver Native PHY IP Core Simulation Support November 2012 Altera Corporation~~
~~PAGE 379~~
16. Transceiver Reconfiguration Controller IP Core The Altera Transceiver Reconfiguration Controller dynamically reconfigures analog settings in Arria V, Cyclone V, and Stratix V devices. Reconfiguration allows you to compensate for variations due to process, voltage, and temperature (PVT) in 28-nm devices. It is required for Arria V, Cyclone V, and Stratix V devices that include transceivers.
~~PAGE 380~~
16–2 Chapter 16: Transceiver Reconfiguration Controller IP Core This user guide describes the features of the Transceiver Reconfiguration Controller. It also includes descriptions of the accessible transceiver registers, information about the MIF file format, and examples demonstrating the update procedures.
~~PAGE 381~~
Chapter 16: Transceiver Reconfiguration Controller IP Core System Overview 16–3 System Overview Figure 16–1 illustrates the Transceiver Reconfiguration Controller’s role. You can include the embedded controller that initiates reconfiguration in your FPGA or use an embedded processor on the PCB. Figure 16–1.
~~PAGE 382~~
16–4 Chapter 16: Transceiver Reconfiguration Controller IP Core Device Family Support 1 ■ For more information about Avalon-MM interfaces including timing diagrams, refer to the Avalon Interface Specifications. Streamer Based —This access mode allows you to either stream a MIF that contains the reconfiguration data or perform direct writes to perform reconfiguration. The streaming mode uses a memory initialization file (.mif) to stream an update to the transceiver PHY IP core. The .
~~PAGE 383~~
Chapter 16: Transceiver Reconfiguration Controller IP Core Performance and Resource Utilization 16–5 Table 16–3. Device Family Support (Part 2 of 2) Device Family Support Stratix V devices Preliminary Other device families No support Performance and Resource Utilization Table 16–4 shows the approximate device resource utilization for a the Transceiver Reconfiguration Controller for Stratix V devices. The numbers of combinational ALUTs and logic registers are rounded to the nearest 50.
~~PAGE 384~~
16–6 Chapter 16: Transceiver Reconfiguration Controller IP Core Parameterizing the Transceiver Reconfiguration Controller IP Core in Qsys 4. Click Finish to generate your customized Transceiver Reconfiguration Controller PHY IP Core. Parameterizing the Transceiver Reconfiguration Controller IP Core in Qsys Complete the following steps to configure the Transceiver Reconfiguration Controller IP Core in Qsys: 1. On the Project Settings tab, select Arria V, Arria V GZ, Cyclone V, or Stratix V from the list.
~~PAGE 385~~
Chapter 16: Transceiver Reconfiguration Controller IP Core Parameterizing the Transceiver Reconfiguration Controller IP Core in Qsys 16–7 Table 16–5. General Options (Part 2 of 2) Name Value Description Transceiver Calibration Functions On When enabled, the Transceiver Reconfiguration Controller includes the offset cancellation functionality. This option is always on. Offset cancellation occurs automatically at power-up and runs only once.
~~PAGE 386~~
~~16–8 Chapter 16: Transceiver Reconfiguration Controller IP Core Interfaces Interfaces Figure 16–2 illustrates the top-level signals of the Transceiver Reconfiguration Controller. Figure 16–2.~~
~~PAGE 387~~
Chapter 16: Transceiver Reconfiguration Controller IP Core Interfaces 16–9 Table 16–6. MIF Reconfiguration Management Avalon-MM Master Interface (Part 2 of 2) Signal Name reconfig_mif_waitrequest Direction Description Input When asserted, indicates that the MIF Avalon-MM slave is not ready to respond to a read request. In Arria V devices, acts as a status port for DCD calibration to prevent simultaneous DCD calibration for multiple channels on the same side of the device.
~~PAGE 388~~
16–10 Chapter 16: Transceiver Reconfiguration Controller IP Core Interfaces Table 16–7. Transceiver Reconfiguration Interface (Part 2 of 2) Signal Name Direction Output tx_cal_busy Output rx_cal_busy Description This optional signal is asserted while calibration is in progress and no further reconfiguration operations should be performed. You can monitor this signal to determine the status of the Transceiver Reconfiguration Controller.
~~PAGE 389~~
Chapter 16: Transceiver Reconfiguration Controller IP Core Transceiver Reconfiguration Controller Memory Map 16–11 Table 16–8. Reconfiguration Management Interface (Part 2 of 2) Signal Name Direction reconfig_mgmt_readdata[31:0] Output Description Output data. reconfig_mgmt_write Input Write signal. Active high. reconfig_mgmt_read Input Read signal. Active high.
~~PAGE 390~~
16–12 Chapter 16: Transceiver Reconfiguration Controller IP Core Transceiver Reconfiguration Controller Calibration Functions Table 16–9 lists the address range for the Transceiver Reconfiguration Controller and the reconfiguration and signal integrity modules. It provides links to the sections describing the registers in each module. Table 16–9.
~~PAGE 391~~
Chapter 16: Transceiver Reconfiguration Controller IP Core PMA Analog Control Registers 16–13 Refer to the Parameterizing the Transceiver Reconfiguration Controller IP Core in the MegaWizard Plug-In Manager section for information about how to enabled these functions.
~~PAGE 392~~
16–14 Chapter 16: Transceiver Reconfiguration Controller IP Core EyeQ Registers f Refer to the Arria V Device Datasheet, the Cyclone V Device Datasheet, or the Stratix V Device Datasheet for more information about the electrical characteristics of each device. The final values are currently pending full characterization of the silicon. 1 All undefined register bits are reserved and must be set to 0. Table 16–11. PMA Offsets and Values Offset 0x0 Bits R/W [5:0] RW Register Name VOD Description VOD.
~~PAGE 393~~
Chapter 16: Transceiver Reconfiguration Controller IP Core EyeQ Registers 16–15 EyeQ uses a phase interpolator and sampler to estimate the vertical and horizontal eye opening using the values that you specify for the horizontal phase and vertical height. (Refer to EyeQ Offsets and Values.) The phase interpolator generates a sampling clock and the sampler examines the data from the receiver output. The sampled data is deserialized and sent to the IP core where the PRBS checker determines the BER.
~~PAGE 394~~
16–16 Chapter 16: Transceiver Reconfiguration Controller IP Core DFE Registers Table 16–13. EyeQ Offsets and Values (Part 2 of 2) Offset 0x2 Bits R/W [5:0] RW [15:14] RMW [13] RW [12:11] RMW Register Name Description Vertical height Taken together, the horizontal phase and vertical height specify the Cartesian x-y coordinates of the point on the eye diagram that you want to sample. You can specify 64 heights on the vertical axis. Reserved You should not modify these bits.
~~PAGE 395~~
Chapter 16: Transceiver Reconfiguration Controller IP Core DFE Registers 1 16–17 If you are using the EyeQ monitor with DFE enabled, you must put the EyeQ monitor in 1D mode by writing the EyeQ 1D-eye bit. For more information, refer to EyeQ Offsets and Values. Table 16–14 lists the direct DFE registers that you can access using Avalon-MM reads and writes on reconfiguration management interface. 1 All undefined register bits are reserved. Table 16–14.
~~PAGE 396~~
16–18 Chapter 16: Transceiver Reconfiguration Controller IP Core Controlling DFE Using Register-Based Reconfiguration Table 16–15. DFE Offset and Values (Part 2 of 2) Offset Bits R/W Register Name Description Specifies the polarity of the third post tap as follows: [3] RW tap 3 polarity 0x3 [2:0] RW tap 3 ■ 0: negative polarity ■ 1: positive polarity Specifies the coefficient for the third post tap. The valid range is 0–7.
~~PAGE 397~~
~~Chapter 16: Transceiver Reconfiguration Controller IP Core Turning on DFE One-Time Adaptation Mode 16–19 Example 16–1the steps to turn on adaptive DFE. Example 16–1.~~
~~PAGE 398~~
16–20 Chapter 16: Transceiver Reconfiguration Controller IP Core Setting the First Tap Value Using DFE in Manual Mode Setting the First Tap Value Using DFE in Manual Mode Complete the following steps to use DFE in Manual mode and set first DFE tap value to 5: 1. Read the DFE control and status register busy bit (bit 8) until it is clear. 2. Write the logical channel number of the channel to be updated to the DFE logical channel number register. 3.
~~PAGE 399~~
Chapter 16: Transceiver Reconfiguration Controller IP Core AEQ Registers 16–21 AEQ Registers Adaptive equalization compensates for backplane losses and dispersion which degrade signal quality. You can choose to run the AEQ once at power up or to run it continuously to dynamically adapt to changing conditions. You can also use AEQ to help control the four-stage continuous time linear equalizer (CTLE) which is a manual tool that compensates for backplane losses and dispersion.
~~PAGE 400~~
16–22 Chapter 16: Transceiver Reconfiguration Controller IP Core ATX PLL Calibration Registers Table 16–17 describes the AEQ registers that you can access to change AEQ settings. 1 All undefined register bits are reserved and must be set to 0. Table 16–17. AEQ Offsets and Values Offset Bits R/W [8] R Description Default Value When asserted, indicates that adaptation has completed.
~~PAGE 401~~
Chapter 16: Transceiver Reconfiguration Controller IP Core PLL Reconfiguration 1 16–23 All undefined register bits are reserved. Table 16–18. ATX Tuning Registers ATX Addr 7’h30 Bits [9:0] R/W RW [9] Register Name logical channel number R 7’h32 control and status Description The logical channel number. The Transceiver Reconfiguration Controller maps the logical address to the physical address. Error. When asserted, indicates an invalid channel or address.
~~PAGE 402~~
16–24 Chapter 16: Transceiver Reconfiguration Controller IP Core PLL Reconfiguration You can establish the number of possible PLL configurations on the Reconfiguration tab of the appropriate transceiver PHY IP core. The Reconfiguration tab allows you to specify up to five input reference clocks and up to four TX PLLs. You can also change the input clock source to the CDR PLL; up to five input clock sources are possible.
~~PAGE 403~~
Chapter 16: Transceiver Reconfiguration Controller IP Core PLL Reconfiguration Registers 16–25 PLL Reconfiguration Registers Table 16–20 lists the PLL reconfiguration registers that you can access using Avalon-MM read and write commands on reconfiguration management interface. PLL reconfiguration is only available for Stratix V devices. 1 All undefined register bits are reserved. Table 16–20.
~~PAGE 404~~
16–26 Chapter 16: Transceiver Reconfiguration Controller IP Core Channel and PLL Reconfiguration Table 16–21 lists the PLL reconfiguration registers. 1 All undefined register bits are reserved and must be set to 0. . Table 16–21. PLL Reconfiguration Offsets and Values Offset 0x0 Bits [2:0] R/W RW Name logical refclk selection Description When written initiates reference clock change to the logical reference clock indexed by bits [2:0].
~~PAGE 405~~
Chapter 16: Transceiver Reconfiguration Controller IP Core Channel and PLL Reconfiguration 16–27 Channel Reconfiguration If you turn on Enable channel/PLL reconfiguration in the Transceiver Reconfiguration Controller GUI, you can change the following channel settings: ■ TX PMA settings ■ RX PMA settings ■ RX CDR input clock ■ Reference clock inputs ■ FPGA fabric transceiver width When you select Enable Channel Interface, in the Custom, Low Latency, Deterministic Latency Transceiver PHY GUIs, the
~~PAGE 406~~
16–28 Chapter 16: Transceiver Reconfiguration Controller IP Core Streamer Module Registers Streamer Module Registers The Streamer module defines the following two modes for channel and PLL reconfiguration: 1 ■ Mode 0—MIF. Uses a memory initialization file (.mif) to reconfigure settings. ■ Mode 1—Direct Write. Uses a series of Avalon-MM writes on the reconfiguration management interface to change settings.
~~PAGE 407~~
Chapter 16: Transceiver Reconfiguration Controller IP Core Streamer Module Registers 16–29 Table 16–23. Streamer Module Registers (Part 2 of 2) PHY Addr 7’h3B 7’h3C Bits [15:0] [31:0] R/W RW RW Register Name Description streamer offset When the MIF mode = 2’b00, the offset register specifies a an internal MIF Streamer register. Refer to Table 16–24 for definitions of these registers.
~~PAGE 408~~
16–30 Chapter 16: Transceiver Reconfiguration Controller IP Core Streamer Module Registers 1 All undefined register bits are reserved and must be set to 0. Table 16–24. Streamer Module Internal MIF Register Offsets Bits Offset 0x0 0x1 [31:0] R/W RW Register Name MIF base address Description Specifies the MIF base address. Writing a 1 to this bit clears any error currently recorded in an indirect register. This register self clears.
~~PAGE 409~~
Chapter 16: Transceiver Reconfiguration Controller IP Core MIF Generation 16–31 Mode 1 Avalon-MM Direct Writes for Reconfiguration You specify this mode by writing a value of 2'b01 into bits 2 and 3 of the control and status register, as indicated in Table 16–23 on page 16–28. In this mode, you can write directly to transceiver PHY IP core registers to perform reconfiguration. Refer to “Direct Write Reconfiguration” on page 16–39 for an example of an update using mode 1.
~~PAGE 410~~
16–32 Chapter 16: Transceiver Reconfiguration Controller IP Core MIF Format You can generate MIF files for projects that include bonded or ATT channels using the following procedure: 1. Create separate 1-channel designs for each frequency TX PLL frequency that your actual design requires. 2. Compile each design with the Quartus II software. 3. Save the MIF files that Quartus II software generates. 4.
~~PAGE 411~~
~~Chapter 16: Transceiver Reconfiguration Controller IP Core xcvr_diffmifgen Utility 16–33 All MIF files must contain the lines shown in Table 16–26. Table 16–26.~~
~~PAGE 412~~
16–34 Chapter 16: Transceiver Reconfiguration Controller IP Core xcvr_diffmifgen Utility Example 16–5 shows the command usage. Example 16–5. xcvr_diffmifgen xcvr_diffmifgen Arguments: -h: Displays help -noopt: The output file is not optimized The format of the reduced MIF file is the same as for the original MIF files as described in MIF Format. The reduced MIF file, preserves the lines shown in Table 16–26. Table 16–27.
~~PAGE 413~~
~~Chapter 16: Transceiver Reconfiguration Controller IP Core Reduced MIF Creation 16–35 Example 16–6 shows part of two MIF files, MIF_A and MIF_B. Line 6, 16, and 20 are different. Example 16–6.~~
~~PAGE 414~~
16–36 Chapter 16: Transceiver Reconfiguration Controller IP Core Changing Transceiver Settings Using Register-Based Reconfiguration You can create a reduced MIF from the following two MIFs: ■ Original MIF—contains the transceiver settings that were specified during the initial compilation ■ Reconfigured MIF—contains the new transceiver settings. You generate the reconfigured MIF by modifying the original transceiver settings.
~~PAGE 415~~
Chapter 16: Transceiver Reconfiguration Controller IP Core Changing Transceiver Settings Using Register-Based Reconfiguration 16–37 7. When busy = 0, the Transceiver Reconfiguration Controller has updated the logical channel specified in Step 2 with the data specified in Step 3. Example 16–8 shows a reconfiguration that changes the logical channel 0 VOD setting to 40. Example 16–8.
~~PAGE 416~~
16–38 Chapter 16: Transceiver Reconfiguration Controller IP Core Changing Transceiver Settings Using Streamer-Based Reconfiguration Changing Transceiver Settings Using Streamer-Based Reconfiguration The Streamer’s registers allow you to change to the PCS datapath settings, clock settings, and PLL parameters by reading the new settings from an on- or off-chip ROM.
~~PAGE 417~~
Chapter 16: Transceiver Reconfiguration Controller IP Core Changing Transceiver Settings Using Streamer-Based Reconfiguration 16–39 Example 16–10 illustrates the reconfiguration of logical channel 0 using a MIF with a base address of 0x100. Example 16–10.
~~PAGE 418~~
16–40 Chapter 16: Transceiver Reconfiguration Controller IP Core Changing Transceiver Settings Using Streamer-Based Reconfiguration In Steps 3 and 4, you must specify an offset value and offset data. You can determine the values of the offset address and offset data by examining the data records specified in either the channel or PLL MIFs. Figure 16–6 shows a sample MIF. Figure 16–6.
~~PAGE 419~~
~~Chapter 16: Transceiver Reconfiguration Controller IP Core Understanding Logical Channel Numbering 16–41 Example 16–11.~~
~~PAGE 420~~
16–42 Chapter 16: Transceiver Reconfiguration Controller IP Core Understanding Logical Channel Numbering Figure 16–8 shows the Low Latency PHY IP ore GUI specifying 32 channels. The message pane indicates that reconfiguration interfaces 0–31 are for the transceiver channels and reconfiguration interfaces 32–63 are for the TX PLLs. Figure 16–8. Low Latency Transceiver PHY Example 1 After Quartus II compilation, many of the interfaces are merged.
~~PAGE 421~~
Chapter 16: Transceiver Reconfiguration Controller IP Core Understanding Logical Channel Numbering 16–43 Figure 16–9 illustrates the GUI for the Transceiver Reconfiguration Controller. To connect the Low Latency PHY IP Core instance to the Transceiver Reconfiguration Controller, you would enter 64 for Number of reconfiguration interfaces. You would not need to enter any values for the Optional interface grouping parameter because all of the interfaces belong to the same transceiver PHY IP core instance.
~~PAGE 422~~
16–44 Chapter 16: Transceiver Reconfiguration Controller IP Core Understanding Logical Channel Numbering Although you must create a separate logical reconfiguration interface for each PHY IP core instance, when the Quartus II software compiles your design, it reduces original number of logical interfaces by merging them. Allowing the Quartus II software to merge reconfiguration interfaces gives the Fitter more flexibility in placing transceiver channels.
~~PAGE 423~~
Chapter 16: Transceiver Reconfiguration Controller IP Core Understanding Logical Channel Numbering 16–45 Table 16–28. Channel Ordering for Concatenated Transceiver Instances Logical Interface Number PHY Instance, Interface, or PLL 0–3 Instance 0, interfaces 0–3. 4-7 Instance 0, TX PLL. The Fitter assigns all 4 logical TX PLLs to a single physical PLL. 8-11 Instance 1, interfaces 0–3. 12-15 Instance 1, TX PLL. The Fitter assigns all 4 logical TX PLLs to a single physical PLL.
~~PAGE 424~~
16–46 Chapter 16: Transceiver Reconfiguration Controller IP Core Understanding Logical Channel Numbering Table 16–30 shows the channel numbers for post-Fitter and hardware simulations. At this point, you should have assigned channels to pins of the device. Table 16–30.
~~PAGE 425~~
Chapter 16: Transceiver Reconfiguration Controller IP Core Transceiver Reconfiguration Controller to PHY IP Connectivity 16–47 Transceiver Reconfiguration Controller to PHY IP Connectivity You can connect a single Transceiver Reconfiguration Controller to all of the transceiver channels and PLLs in your design. You can also use multiple Transceiver Reconfiguration Controllers to facilitate placement and routing of the FPGA.
~~PAGE 426~~
16–48 Chapter 16: Transceiver Reconfiguration Controller IP Core Merging TX PLLs In Multiple Transceiver PHY Instances Merging TX PLLs In Multiple Transceiver PHY Instances The Quartus II Fitter can merge the TX PLLs for multiple transceiver PHY IP cores under the following conditions: ■ The PLLs connect to the same reset pin. ■ The PLLs connect to the same reference clock. ■ The PLLs connect to the same Transceiver Reconfiguration Controller.
~~PAGE 427~~
Chapter 16: Transceiver Reconfiguration Controller IP Core Loopback Modes 16–49 Loopback Modes You can enable the pre- and post-CDR reverse serial loopback modes by writing the appropriate bits of the Transceiver Reconfiguration Controller pma_offset register described in PMA Analog Registers. In pre-CDR mode, data received through the RX input buffer is looped back to the TX output buffer. In post-CDR mode, received data passes through the RX CDR and then loops back to the TX output buffer.
~~PAGE 428~~
16–50 Chapter 16: Transceiver Reconfiguration Controller IP Core Loopback Modes Figure 16–15 shows the datapath for serial loopback. The data from the FPGA fabric passes through the TX channel and is looped back to the RX channel, bypassing the RX buffer. The received data is available to the FPGA fabric for verification. Using the serial loopback option, you can check the operation of all enabled PCS and PMA functional blocks in the TX and RX channels.
~~PAGE 429~~
17. Transceiver PHY Reset Controller IP Core The Transceiver PHY Reset Controller IP Core is a highly configurable core that you can use to reset transceivers in Arria V, Cyclone V, or Stratix V devices. This reset controller is an alternate controller that you can use instead of the embedded reset controller for the Custom, Low Latency, and Deterministic Latency PHY IP cores.
~~PAGE 430~~
Chapter 17: Transceiver PHY Reset Controller IP Core Device Family Support 17–2 As Figure 17–1 illustrates, the Transceiver PHY Reset Controller connects to a Transceiver PHY. The Transceiver PHY Reset Controller IP Core drives TX and RX resets to the Transceiver PHY and receives status from the Transceiver PHY. Depending on the components in the design, the calibration busy signal may be an output of the Transceiver PHY or the Transceiver Reconfiguration Controller.
~~PAGE 431~~
Chapter 17: Transceiver PHY Reset Controller IP Core Performance and Resource Utilization 17–3 Performance and Resource Utilization Table 17–2 shows the typical expected device resource utilization, rounded to the nearest 50, for two configurations using the current version of the Quartus II software targeting a Stratix V GX device. Figures are rounded to the nearest 50. Table 17–2.
~~PAGE 432~~
Chapter 17: Transceiver PHY Reset Controller IP Core Transceiver PHY Reset Controller Parameters 17–4 Table 17–3. General Options (Part 2 of 3) Name Range Description TX PLL Enable TX PLL channel reset control pll_powerdown duration Synchronize reset input for PLL powerdown On/Off When On, the Transceiver PHY Reset Controller enables the control of the TX PLL. When Off, the TX PLL controls are disabled. 1–999999999 Specifies the duration of the PLL powerdown period in ns.
~~PAGE 433~~
Chapter 17: Transceiver PHY Reset Controller IP Core Interfaces 17–5 Table 17–3. General Options (Part 3 of 3) Name Use separate RX reset per channel Range Description On/Off When On, each RX channel has a separate reset input. When Off, uses a shared RX reset controller for all channels. Specifies the Transceiver PHY Reset Controller behavior when the pll_locked signal is deasserted.
~~PAGE 434~~
Chapter 17: Transceiver PHY Reset Controller IP Core Interfaces 17–6 Table 17–4 describes the signals in Figure 17–2 in the order that they are shown in the figure. Table 17–4. Top-Level Signals (Part 1 of 2) Signal Name Direction Description Input Signals pll_locked[
~~-1:0] Input Provides the PLL locked status input for each PLL. When asserted, indicates that the TX PLL is locked. When deasserted, the PLL is not locked. There is one signal per PLL.~~
~~PAGE 435~~
Chapter 17: Transceiver PHY Reset Controller IP Core Interfaces 17–7 Table 17–4. Top-Level Signals (Part 2 of 2) Signal Name Direction Input reset Description Asynchronous reset input to the Transceiver PHY Reset Controller. When asserted, all configured reset outputs are asserted. Holding the reset input signal asserted holds all other reset outputs asserted. Output Signals Digital reset for TX. The width of this signal depends on the number of TX channels.
~~PAGE 436~~
17–8 Chapter 17: Transceiver PHY Reset Controller IP Core Timing Constraints for Reset Signals when Using Bonded PCS Channels Timing Constraints for Reset Signals when Using Bonded PCS Channels For designs that use bonded TX PCS channels, the reset signal to all TX PCS channels within a bonded group must meet a maximum skew tolerance. This skew tolerance is one-half the TX parallel clock cycle.
~~PAGE 437~~
18. Analog Parameters Set Using QSF Assignments You specify the analog parameters using the Quartus II Assignment Editor, the Pin Planner, or through the Quartus II Settings File (.qsf). The default values for analog options fall into three categories: ■ Global— These parameters have default values that are independent of other parameter settings. ■ Computed—These parameters have an initial default value that is recomputed based on other parameter settings.
~~PAGE 438~~
18–2 Chapter 18: Analog Parameters Set Using QSF Assignments Analog Settings for Arria V Devices Analog Settings for Arria V Devices Table 18–1 lists the analog parameters for Arria V devices whose original values are place holders for the values that match your electrical board specification. In Table 18–1, the default value of an analog parameter is shown in bold type. The parameters are listed in alphabetical order. Table 18–1.
~~PAGE 439~~
Chapter 18: Analog Parameters Set Using QSF Assignments Analog Settings for Arria V Devices 18–3 Table 18–1. Transceiver and PLL Assignments for Arria V Devices (Part 2 of 2) Pin Planner and Assignment Editor Name QSF Assignment Name Description Options Assign To 1–5 Pin TX serial data Specifies the slew rate of the output signal.
~~PAGE 440~~
18–4 Chapter 18: Analog Parameters Set Using QSF Assignments Analog Settings for Arria V Devices Table 18–2. Transceiver and PLL Assignments for Arria V Devices (Part 2 of 2) QSF Assignment Name Pin Planner and Assignment Editor Name Receiver Signal Detection Unit Enable/Disable XCVR_RX_SD_ENABLE Description Options Assign To Enables or disables the receiver signal detection unit. During normal operation NORMAL_SD_ON=false, otherwise POWER_DOWN_SD=true. For the PCIe PIPE PHY.
~~PAGE 441~~
Chapter 18: Analog Parameters Set Using QSF Assignments Analog Settings for Arria V GZ Devices 18–5 Analog Settings for Arria V GZ Devices Table 18–3 lists the analog parameters for Arria V GZ devices whose original values are place holders for the values that match your electrical board specification. In Table 18–3, the default value of an analog parameter is shown in bold type. The parameters are listed in alphabetical order. Table 18–3.
~~PAGE 442~~
18–6 Chapter 18: Analog Parameters Set Using QSF Assignments Analog Settings for Arria V GZ Devices Table 18–3. Transceiver and PLL Assignments for Arria V GZ Devices (Part 2 of 2) QSF Assignment Name XCVR_TX_SLEW_RATE_CTRL Pin Planner and Assignment Editor Name Transmitter Slew Rate Control VCCA_GXB Voltage XCVR_VCCA_VOLTAGE XCVR_VCCR_VCCT_VOLTAGE VCCR_GXB VCCT_GXB Voltage Description Options Assign To Specifies the slew rate of the output signal.
~~PAGE 443~~
~~Chapter 18: Analog Parameters Set Using QSF Assignments Analog Settings for Arria V GZ Devices 18–7 Table 18–4.~~
~~PAGE 444~~
~~18–8 Chapter 18: Analog Parameters Set Using QSF Assignments Analog Settings for Arria V GZ Devices Table 18–4.~~
~~PAGE 445~~
Chapter 18: Analog Parameters Set Using QSF Assignments Analog Settings for Arria V GZ Devices 18–9 Table 18–4. Transceiver and PLL Assignments for Arria V GZ Devices (Part 4 of 4) QSF Assignment Name Pin Planner and Assignment Editor Name Description Options Assign To XCVR_TX_PRE_EMP_INV_ PRE_TAP Transmitter Preemphasis Pre Tap Invert Inverts the transmitter pre-emphasis pre-tap.
~~PAGE 446~~
18–10 Chapter 18: Analog Parameters Set Using QSF Assignments Analog Settings for Cyclone V Devices Analog Settings for Cyclone V Devices Table 18–5 lists the analog parameters for Cyclone V devices whose original values are place holders for the values that match your electrical board specification. In Table 18–5, the default value of an analog parameter is shown in bold type. The parameters are listed in alphabetical order. Table 18–5.
~~PAGE 447~~
Chapter 18: Analog Parameters Set Using QSF Assignments Analog Settings for Cyclone V Devices 18–11 Table 18–5. Transceiver and PLL Assignments for Cyclone V Devices (Part 2 of 2) Pin Planner and Assignment Editor Name QSF Assignment Name Description Options Assign To 1–5 Pin TX serial data 1_1V 1_2V Pin TX & RX serial data Specifies the slew rate of the output signal.
~~PAGE 448~~
18–12 Chapter 18: Analog Parameters Set Using QSF Assignments Analog Settings for Cyclone V Devices Table 18–6. Transceiver and PLL Assignments for Cyclone V Devices (Part 2 of 2) QSF Assignment Name Pin Planner and Assignment Editor Name Receiver Signal Detection Unit Enable/Disable XCVR_RX_SD_ENABLE Description Options Assign To Enables or disables the receiver signal detection unit. During normal operation NORMAL_SD_ON=false, otherwise POWER_DOWN_SD=true.For the PCIe PIPE PHY.
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Chapter 18: Analog Parameters Set Using QSF Assignments Analog Settings for Stratix V Devices 18–13 Analog Settings for Stratix V Devices Table 18–7 lists the analog parameters for Stratix V devices whose original values are place holders for the values that match your electrical board specification. In Table 18–7, the default value of an analog parameter is shown in bold type. The parameters are listed in alphabetical order. Table 18–7.
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18–14 Chapter 18: Analog Parameters Set Using QSF Assignments Analog Settings for Stratix V Devices Table 18–7. Transceiver and PLL Assignments for Stratix V Devices (Part 2 of 2) Pin Planner and Assignment Editor Name Description XCVR_RX_BYPASS_EQ_ STAGES_234 Receiver Equalizer Stage 2, 3, 4 Bypass Bypass continuous time equalizer stages 2, 3, and 4 to save power. This setting eliminates significant AC gain on the equalizer and is appropriate for chip-to-chip short range communication on a PCB.
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Chapter 18: Analog Parameters Set Using QSF Assignments Analog Settings for Stratix V Devices 18–15 Table 18–8. Transceiver and PLL Assignments for Stratix V Devices (Part 2 of 5) Pin Planner and Assignment Editor Name QSF Assignment Name Description Options Assign To XCVR_RX_DC_GAIN Receiver Buffer DC Gain Control Controls the RX buffer DC gain for GX channels.
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18–16 Chapter 18: Analog Parameters Set Using QSF Assignments Analog Settings for Stratix V Devices Table 18–8. Transceiver and PLL Assignments for Stratix V Devices (Part 3 of 5) QSF Assignment Name Pin Planner and Assignment Editor Name Description Options Assign To XCVR_GT_TX_PRE_EMP_INV_ PRE_TAP GT Transmitter Preemphasis Pre Tap Invert Inverts the transmitter pre-emphasis pre-tap. This parameter is only for GT transceivers.
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Chapter 18: Analog Parameters Set Using QSF Assignments Analog Settings for Stratix V Devices 18–17 Table 18–8. Transceiver and PLL Assignments for Stratix V Devices (Part 4 of 5) QSF Assignment Name XCVR_RX_SD_ON Pin Planner and Assignment Editor Name Description Options Assign To Receiver Cycle Count Before Signal Detect Block Declares Presence Of Signal Number of parallel cycles to wait before the signal detect block declares presence of signal. For the PCIe PIPE PHY.
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18–18 Chapter 18: Analog Parameters Set Using QSF Assignments Analog Settings for Stratix V Devices Table 18–8. Transceiver and PLL Assignments for Stratix V Devices (Part 5 of 5) QSF Assignment Name Pin Planner and Assignment Editor Name Description Options Assign To XCVR_TX_PRE_EMP_2ND_ POST_TAP Transmitter Preemphasis Second Post-Tap Specifies the second post-tap setting value.
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19. Migrating from Stratix IV to Stratix V Devices Previously, Altera provided the ALTGX megafunction as a general purpose transceiver PHY solution. The current release of the Quartus II software includes protocol-specific PHY IP cores that simplify the parameterization process. The design of these protocol-specific transceiver PHYs is modular and uses standard interfaces. An Avalon-MM interface provides access to control and status registers that record the status of the PCS and PMA modules.
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19–2 Chapter 19: Migrating from Stratix IV to Stratix V Devices Differences in Dynamic Reconfiguration for Stratix IV and Stratix V Transceivers Differences in Dynamic Reconfiguration for Stratix IV and Stratix V Transceivers Dynamic reconfiguration interface is completely new in Stratix V devices. You cannot automatically migrate a dynamic reconfiguration solution from Stratix IV to Stratix V devices.
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Chapter 19: Migrating from Stratix IV to Stratix V Devices Differences Between XAUI PHY Parameters for Stratix IV and Stratix V Devices 19–3 Differences Between XAUI PHY Parameters for Stratix IV and Stratix V Devices Table 19–2 lists the XAUI PHY parameters and the corresponding ALTGX megafunction parameters. Table 19–2.
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19–4 Chapter 19: Migrating from Stratix IV to Stratix V Devices Differences Between XAUI PHY Ports in Stratix IV and Stratix V Devices Differences Between XAUI PHY Ports in Stratix IV and Stratix V Devices Table 19–5 lists the differences between the top-level signals in Stratix IV GX and Stratix V GX/GS devices. Table 19–3.
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~~Chapter 19: Migrating from Stratix IV to Stratix V Devices Differences Between PHY IP Core for PCIe PHY (PIPE) Parameters in Stratix IV and Stratix V Devices 19–5 Table 19–3.~~
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~~19–6 Chapter 19: Migrating from Stratix IV to Stratix V Devices Differences Between PHY IP Core for PCIe PHY (PIPE) for Stratix IV and Stratix V Devices Table 19–4.~~
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Chapter 19: Migrating from Stratix IV to Stratix V Devices Differences Between PHY IP Core for PCIe PHY (PIPE) for Stratix IV and Stratix V Devices 19–7 Table 19–5. PCIe PHY (PIPE) Correspondence between Stratix IV GX Device and Stratix V Device Signals (Part 2 of 3) Stratix IV GX Device Signal Name pll_powerdown cal_blk_powerdown Stratix V Device Signal Name Width These signals are now available as control and status registers.
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~~19–8 Chapter 19: Migrating from Stratix IV to Stratix V Devices Differences Between PHY IP Core for PCIe PHY (PIPE) for Stratix IV and Stratix V Devices Table 19–5.~~
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Chapter 19: Migrating from Stratix IV to Stratix V Devices Differences Between Custom PHY Parameters for Stratix IV and Stratix V Devices 19–9 Differences Between Custom PHY Parameters for Stratix IV and Stratix V Devices Table 19–6 lists the Custom PHY parameters and the corresponding ALTGX megafunction parameters. Table 19–6.
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~~19–10 Chapter 19: Migrating from Stratix IV to Stratix V Devices Differences Between Custom PHY Ports in Stratix IV and Stratix V Devices Table 19–6.~~
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Chapter 19: Migrating from Stratix IV to Stratix V Devices Differences Between Custom PHY Ports in Stratix IV and Stratix V Devices 19–11 Table 19–7. Custom PHY Correspondences between Stratix IV GX Device and Stratix V Device Signals (Part 2 of 2) rx_freqlocked rx_is_lockedtodata [-1:0] Transceiver Control and Status Signals gxb_powerdown phy_mgmt_clk_reset rx_dataoutfull — tx_dataoutfull — rx_pll_locked There are both pll_locked and rx_pll_clocked in Stratix IV.
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19–12 Altera Transceiver PHY IP Core User Guide Chapter 19: Migrating from Stratix IV to Stratix V Devices Differences Between Custom PHY Ports in Stratix IV and Stratix V Devices November 2012 Altera Corporation
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Additional Information This chapter provides additional information about the document and Altera. Revision History The table below displays the revision history for the chapters in this user guide. Date Version Changes Made Introduction and Getting Started November 2012 ■ Expanded discussion of the Arria V, Arria V GZ, Cyclone V, and Stratix V Transceiver Native PHY IP Cores. ■ Added Riviera-PRO aldec simulation directory. 1.8 10GBASE-R PHY November 2012 1.
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20–2 Additional InformationAdditional Information Revision History Date Version Changes Made PHY IP Core for PCI Express (PIPE) November 2012 1.8 ■ Added Gen3 support. ■ Added Arria V GZ support. ■ Added ×2 support. ■ Added discussion of link equalization for Gen3. ■ Added timing diagram showing rate change to Gen3. ■ Revised presentation of signals. ■ Corrected the definition of rx_eidleinfersel[3-1:0]. ■ Moved Analog Options to a separate chapter.
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Additional InformationAdditional Information Revision History Date 20–3 Version Changes Made Cyclone V Transceiver Native PHY November 2012 1.8 ■ Initial release. Reconfiguration Controller November 2012 1.8 ■ Added MIF addressing mode option. Byte and word (16 bits) addressing are available. ■ Added ATX PLL reference clock switching and reconfiguration of ATX PLL settings, including counters. ■ Added support for ATX PLL reconfiguration.
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20–4 Additional InformationAdditional Information Revision History Date Version Changes Made 10GBASE-R June 2012 ■ Added the following QSF settings to all transceiver PHY: XCVR_TX_PRE_EMP_PRE_TAP_USER, XCVR_TX_PRE_EMP_2ND_POST_TAP_USER, and 11 new settings for GT transceivers. ■ Added Arria V device support. ■ Changed the default value for XCVR_REFCLK_PIN_TERMINATION from DC_coupling_internal_100_Ohm to AC_coupling. ■ Changed references to Stratix IV GX to Stratix IV GT.
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Additional InformationAdditional Information Revision History Date 20–5 Version Changes Made Interlaken June 2012 1.7 ■ Added support for custom, user-defined, data rates. ■ Added the following QSF settings to all transceiver PHY: XCVR_TX_PRE_EMP_PRE_TAP_USER, XCVR_TX_PRE_EMP_2ND_POST_TAP_USER, and 11 new settings for GT transceivers. ■ Changed the default value for XCVR_REFCLK_PIN_TERMINATION from DC_coupling_internal_100_Ohm to AC_coupling. ■ Updated the definition of tx_sync_done.
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20–6 Additional InformationAdditional Information Revision History Date Version Changes Made Custom Transceiver PHY June 2012 1.7 ■ Added the following QSF settings to all transceiver PHY: XCVR_TX_PRE_EMP_PRE_TAP_USER, XCVR_TX_PRE_EMP_2ND_POST_TAP_USER, and 11 new settings for GT transceivers. ■ Added reference to Stratix V Transceiver Architecture chapter for detailed explanation of the PCS blocks.
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Additional InformationAdditional Information Revision History Date 20–7 Version Changes Made Deterministic Latency June 2012 1.7 ■ Added the following QSF settings to all transceiver PHY: XCVR_TX_PRE_EMP_PRE_TAP_USER, XCVR_TX_PRE_EMP_2ND_POST_TAP_USER, and 11 new settings for GT transceivers. ■ Added PLL reconfiguration option. ■ Changed the default value for XCVR_REFCLK_PIN_TERMINATION from DC_coupling_internal_100_Ohm to AC_coupling.
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20–8 Additional InformationAdditional Information Revision History Date Version Changes Made 10GBASE-R February 2012 ■ Added datapath latency numbers for Stratix V devices. ■ Corrected bit range for ERRORED_BLOCK_COUNT. ■ Added statement that the the cal_blk_powerdown (0x021) and pma_tx_pll_is_locked (0x022) registers are only available when the Use external PMA control and reconfig option is turned On on the Additional Options tab of the GUI.
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Additional InformationAdditional Information Revision History Date 20–9 Version Changes Made Interlaken December 2011 1.4 ■ Changed access mode for RX equalization, pre-CDR reverse serial loopback, and post-CDR reverse serial loopback to write only (WO). ■ Removed optional rx_sync_word_err, rx_scrm_err, and rx_framing_err status bits. ■ Changed definition of phy_mgmt_clk_reset. This signal is active high and level sensitive. PHY IP Core for PCI Express (PIPE) December 2011 1.
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20–10 Additional InformationAdditional Information Revision History Date Version Changes Made Introduction November 2011 ■ Revised reset section. The 2 options for reset are now the embedded reset controller or user-specified reset controller. ■ Updated directory names in simulation testbench. 1.3 10GBASE-R PHY Transceiver November 2011 1.3 ■ Added support for Stratix V devices. ■ Added section discussing transceiver reconfiguration in Stratix V devices.
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Additional InformationAdditional Information Revision History Date 20–11 Version Changes Made Low Latency PHY November 2011 ■ Added base data rate, lane rate, input clock frequency, and PLL type parameters. ■ Updated QSF settings to include text strings used to assign values and location of the assignment which is either a pin or PLL. ■ Revised reset options. The 2 options for reset are now the embedded reset controller or a user-specified reset logic. 1.
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20–12 Additional InformationAdditional Information Revision History Date May 2011 Version 1.2 Changes Made ■ Added simulation section. ■ Revised Figure 1–1 on page 1–1 to show the Transceiver Reconfiguration Controller as a separately instantiated IP core. ■ Added statement saying that the transceiver PHY IP cores do not support the NativeLink feature of the Quartus II software. ■ Revised reset section. Getting Started May 2011 1.2 ■ No changes from previous release.
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Additional InformationAdditional Information Revision History Date 20–13 Version Changes Made Interlaken PHY Transceiver May 2011 ■ Added details about the 0 ready latency for tx_ready. ■ Added PLL support to lane rate parameter description in Interlaken PHY General Options. ■ Moved dynamic reconfiguration for the transceiver outside of the Interlaken PHY IP Core. The reconfiguration signals now connect to a separate Reconfiguration Controller IP Core.
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20–14 Additional InformationAdditional Information Revision History Date Version Changes Made Transceiver Reconfiguration Controller May 2011 ■ Added Stratix V support. The Transceiver Reconfiguration Controller is only available for Stratix IV devices in the Transceiver Toolkit. ■ Added sections describing the number of reconfiguration interfaces required and restrictions on channel placement. ■ Added pre- and post-serial loopback controls. ■ Changed reconfiguration clock source. In 10.
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Additional InformationAdditional Information Revision History Date Version 20–15 Changes Made XAUI PHY Transceiver December 2010 1.1 ■ Added support for Arria II GX and Cyclone IV GX with hard PCS ■ Renamed management interface, adding phy_ prefix ■ Changed phy_mgmt_address from 16 to 9 bits. ■ Renamed many signals. Refer to XAUI Top-Level Signals—Soft PCS and PMA and “XAUI Top-Level Signals–Hard IP PCS and PMA” as appropriate.
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20–16 Additional InformationAdditional Information How to Contact Altera Date Version Changes Made Transceiver Reconfiguration Controller December 2010 1.1 ■ Reconfiguration is now integrated into the XAUI PHY IP Core and 10GBASE-R PHY IP Core. ■ Revised register map to show word addresses instead of a byte offset from a base address. Migrating from Stratix IV to Stratix V December 2010 November 2010 July 2010 1.1 1.1 1.0 ■ Changed phy_mgmt_address from 16 to 9 bits.
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Additional InformationAdditional Information Typographic Conventions Visual Cue 20–17 Meaning Indicates variables. For example, n + 1. italic type Variable names are enclosed in angle brackets (< >). For example, and .pof file. Initial Capital Letters Indicate keyboard keys and menu names. For example, the Delete key and the Options menu. “Subheading Title” Quotation marks indicate references to sections in a document and titles of Quartus II Help topics.
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~~20–18 Altera Transceiver PHY IP Core User Guide Additional InformationAdditional Information Typographic Conventions November 2012 Altera Corporation~~