User guide

Chapter 5: 1G/10 Gbps Ethernet PHY IP Core 5–18
Dynamic Reconfiguration from 1G to 10GbE
November 2012 Altera CorporationAltera Transceiver PHY IP Core
User Guide
Arbitration Logic Requirements
The arbiter shown in Figure 5–4 should implement the following logic. You can
modify this logic based on your system requirements:
1. Accept requests from either the sequencer (if Enable automatic speed detection is
turned On in the GUI) or user logic. Prioritize requests to meet system
requirements. Requests should consist of the following two buses:
a. Channel number—specifies the requested channel.
b. Mode—specifies 1G or 10G mode for the corresponding channel
2. Select a channel for reconfiguration and send an
ack/busy signal to the requestor.
The requestor should deassert its request signal when the
ack/busy is received.
3. Pass the selected channel and rate information to the state machine for processing.
4. Wait for a done signal from the state machine indicating that the reconfiguration
process is complete and it is ready to service another request.
Figure 5–4. Block Diagram for Reconfiguration Example
1G/10Gb
Ethernet
MAC
1G/10Gb Ethernet PHY MegaCore Function
1G/10Gb Ethernet PHY MegaCore Function
1G/10Gb Ethernet PHY MegaCore Function
Native PHY Hard IP
257.8
MHz
40-b
40-b
TX
Serial
Data
RX
Serial
Data
322.265625 or
644.53125
Ref Clk
62.5 or 125
Ref Clk
ATX/CMU
TX PLL
For
10 GbE
ATX/CMU
TX PLL
For 1 GbE
1.25 Gb/
10.3125 Gb
Hard PMA
Link
Status
Sequencer
S
Reset
Controller
State
Machine
Arbiter
rate change request
ack to user
rate change
req from user
Transceiver
Reconfig
Controller
10 Gb
Ethernet
Hard PCS
Cntl &
Status
RX GMII Data
TX GMII Data
@ 125 MHz
RX XGMII Data
TX XGMII Data
Shared Across Multiple Channels
Can Share
Across Multiple
Channels
@156.25 MHz
1 GIGE
PCS
1G/10Gb
Ethernet
MAC
1G/10Gb
Ethernet
MAC
1G
10G
1 Gb
Ethernet
Standard
Hard PCS