User guide

Chapter 5: 1G/10 Gbps Ethernet PHY IP Core 5–23
Simulation
November 2012 Altera CorporationAltera Transceiver PHY IP Core
User Guide
Simulation
The 1G/10GbE PHY IP Core support ModelSim Verilog and ModelSim VHDL, VCS
Verilog, and VCS VHDL simulation. Stratix V devices also support NCSIM Verilog
and MCSIM VHDL simulation. The MegaWizard Plug-In Manager generates an IP
functional simulation model when you press the Finish button.
TimeQuest Timing Constraints
To pass timing analysis, you must decouple the clocks in different time domains. The
necessary Synopsys Design Constraints File (.sdc) timing constraints for the
1G/10GbE IP Core are included in the top-level wrapper file.
Acronyms
Table 5–20 lists commonly used acronyms for the 1G/10GbE PHY IP Core.
Table 5–20. Common Ethernet Acronyms
Acronym Definition
AN Auto-Negotiation in Ethernet as described in Clause 73 or of IEEE 802.3ap-2007.
BER Bit Error Rate.
DME Differential Manchester Encoding.
FEC Forward error correction.
GMII Gigabit Media Independent Interface.
KR Short hand notation for Backplane Ethernet with 64b/66b encoding.
LD Local Device.
LT
Link training in backplane Ethernet Clause 72 for 10GBASE-KR and
40GBASE-KR4.
LP Link partner, to which the LD is connected.
MAC Media Access Control.
MII Media independent interface.
OSI Open System Interconnection.
PCS Physical Coding Sublayer.
PHY
Physical Layer in OSI 7-layer architecture, also in Altera device scope is: PCS +
PMA.
PMA Physical Medium Attachment.
PMD Physical Medium Dependent.
SGMII Serial Gigabit Media Independent Interface.
WAN Wide Area Network.
XAUI 10 Gigabit Attachment Unit Interface.