User guide

6–8 Chapter 6: XAUI PHY IP Core
Configurations
Altera Transceiver PHY IP Core November 2012 Altera Corporation
User Guide
Configurations
Figure 6–2 illustrates one configuration of the XAUI IP Core. As this figure illustrates,
if your variant includes a single instantiation of the XAUI IP Core, the transceiver
reconfiguration control logic is included in the XAUI PHY IP Core. For Arria V,
Cyclone V, and Stratix V devices the Transceiver Reconfiguration Controller must
always be external. Refer to Chapter 16, Transceiver Reconfiguration Controller IP
Core for more information about this IP core.
Ports
Figure 6–3 illustrates the top-level signals of the XAUI PHY IP Core for the hard IP
implementation. Figure 6–4 illustrates the top-level signals of the XAUI PHY IP Core
for the soft IP implementation. With the exception of the optional signals available for
debugging and the signals for dynamic reconfiguration of the transceivers, the
top-level signals of the two variants is nearly identical. The DDR XAUI soft IP signals
and behavior are the same as the soft IP implementation.
Figure 6–2. XAUI PHY with Internal Transceiver Reconfiguration Control
Note to Figure6–2:
(1) The Transceiver Reconfiguration Controller is always a separately instantiated in Stratix V devices.
System
Interconnect
Fabric
Inter-
leave
PCS
S
Alt_PMA
S
S
Low Latency
Controller
S
Transceiver
Reconfiguration
Controller
Transceiver Channel
Hard XAUI PHY
4 x 3.125 Gbps serial
to Embedded
Controller
4
4
To MAC
SDR XGMII
72 bits @ 156.25 Mbps
M
Avalon-MM
PHY
Mgmt
S
PMA Channel
Controller