User guide

7–8 Chapter 7: Interlaken PHY IP Core
Avalon-ST RX Interface
Altera Transceiver PHY IP Core November 2012 Altera Corporation
User Guide
Avalon-ST RX Interface
Table 7–5 describes the signals in the Avalon-ST RX interface.
tx_user_clkout Output
For single lane Interlaken links,
tx_user_clkout is available when
you do not create the optional
tx_coreclkin . For Interlaken links
with more than 1 lane,
tx_coreclkin is required and
tx_user_clkout cannot be used. tx_coreclkin must have a
minimum frequency of the lane data rate divided by 67. The frequency
range for
tx_coreclkin is (data rate/40) – (data rate/67). For best
results, Altera recommends that
rx_coreclkin = (data rate/40).
pll_locked Output
In multilane Interlaken designs, this signal is the bitwise
AND of the
individual lane
pll_locked signals. This output is synchronous to the
phy_mgmt_clk clock domain.
tx_sync_done Output
When asserted, indicates that all
tx_parallel_data lanes are
synchronized and ready for valid user data traffic. The Interlaken MAC
must wait for this signal to be asserted before initiating valid user data
transfers on any lane. This output is synchronous to the
tx_coreclkin clock domain. For consistent tx_sync_done
performance, Altera recommends using
tx_coreclkin and
rx_coreclkin frequency of lane (data rate/40).
You must invoke a hard reset using
mgmt_rst_reset and
phy_mgmt_clk_reset to initiate the synchronization sequence on the
TX lanes.
For Quartus versions prior to 12.0, you must pre-fill the TX FIFO
before
tx_sync_done can be asserted. Use the following Verilog HDL
assignment for Quartus II releases prior to 12.0:
assign tx_parallel_data[65] =
(!tx_sync_done)?1'b1:tx_datain_bp[0];
Table 7–4. Avalon-ST TX Signals (Part 3 of 3)
Signal Name Direction Description
Table 7–5. Avalon-ST RX Signals (Part 1 of 4)
Signal Name Direction Description
rx_parallel_data<n>[63:0] Output
Avalon-ST data bus driven from the RX PCS to the FPGA fabric. This
output is synchronous to the
rx_coreclkin clock domain.
rx_parallel_data<n>[64] Output
When asserted, indicates that
rx_parallel_data<n>[63:0] is
valid. When deasserted, indicates the
rx_parallel_data<n>[63:0] is invalid. This output is
synchronous to the
rx_coreclkin clock domain.
The Interlaken PCS implements a gearbox between the PMA and PCS
interface. The
rx_parallel_data<n>[64] port is deasserted
whenever the gearbox is in the invalid region. The Interlaken MAC
should not read
rx_parallel_data<n>[65, 63:0] if
rx_parallel_data<n>[64] is deasserted.