User guide

7–10 Chapter 7: Interlaken PHY IP Core
Avalon-ST RX Interface
Altera Transceiver PHY IP Core November 2012 Altera Corporation
User Guide
rx_parallel_data<n>[69] Output
When asserted, indicates that the RX FIFO has found the first
Interlaken synchronization word alignment pattern. For very short
metaframes, this signal may be asserted after the frame synchronizer
state machine validates frame synchronization and asserts
rx_parallel_data<n>[70] because this signal is asserted by the
RX FIFO which is the last PCS block in the RX datapath. This output
is synchronous to the rx_coreclkin clock domain.
This signal is optional. If the RX PCS FIFO reaches the empty state or
is in an empty state,
rx_parallel_data<n>[70] indicating
metaframe lock and
rx_parallel_data<n>[69] indicating that the
first Interlaken synchronization word alignment pattern has been
received remain asserted, but
rx_parallel_data<n>[66] block
lock and frame lock status signal are deasserted in the next clock
cycle.
rx_parallel_data<n>[70] Output
When asserted, indicates that the RX frame synchronization state
machine has found and received 4 consecutive, valid synchronization
words. The frame synchronization state machine requires 4
consecutive synchronization words to exit the presync state and
enter the synchronized state. You should only use this optional signal
as a secondary status flag. The
rx_parallel_data[66] signal
should be used as the primary frame synchronization status flag.
This output is synchronous to the rx_clkout clock domain.
This signal is optional. If the RX PCS FIFO reaches an empty state or
is in an empty state,
rx_parallel_data<n>[70] indicating
metaframe lock and
rx_parallel_data<n>[69] indicating that the
first Interlaken synchronization word alignment pattern has been
received remain asserted but
rx_parallel_data<n>[66] block
lock and frame lock status signal are deasserted in the next clock
cycle.
rx_parallel_data<n>[71] Output
When asserted, indicates a CRC32 error in this lane. This signal is
optional. This output is synchronous to the rx_clkout clock domain.
rx_ready Output
When asserted, indicates that the RX interface has exited the reset
state and is ready for service. The Interlaken MAC must wait for
rx_ready to be asserted before initiating data transfer on any lanes.
This output is synchronous to the
phy_mgmt_clk domain.
rx_clkout Output
Output clock from the RX PCS. The frequency of this clock equals the
Lane rate divided by 40, which is the PMA serialization factor.
rx_fifo_clr<n> Input
When asserted, the RX FIFO is flushed. This signal allows you to
clear the FIFO if the receive FIFO overflows or if the Interlaken MAC is
not able to achieve multi-lane alignment in the Interlaken MAC's
deskew state machine. The
rx_fifo_clr signal must be asserted
for 4
rx_clkout cycles to successfully flush the RX FIFO.
This output is synchronous to the
rx_clkout clock domain.
Table 7–5. Avalon-ST RX Signals (Part 3 of 4)
Signal Name Direction Description