User guide

Chapter 8: PHY IP Core for PCI Express (PIPE) 8–3
Parameterizing the PHY IP Core for PCI Express (PIPE)
November 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
Parameterizing the PHY IP Core for PCI Express (PIPE)
Complete the following steps to configure the PHY IP Core for PCI Express in the
MegaWizard Plug-In Manager:
1. For Which device family will you be using?, select Arria V GZ or Stratix V.
2. Click Installed Plug-Ins > Interfaces > PCI Express > PHY IP Core for PCI
Express (PIPE) v12.1.
3. Use the tabs on the MegaWizard Plug-In Manager to select the options required
for the protocol.
4. Refer to the General Options Parameters to learn more about the parameters.
5. Click Finish to generate your customized PHY IP Core for PCI Express variant.
General Options Parameters
This section describes the PHY IP Core for PCI Express parameters, which you can set
using the MegaWizard Plug-In Manager. Table 8–2 lists the settings available on
General Options tab.
Table 8–2. PHY IP Core for PCI Express General Options (Part 1 of 2)
Name Value Description
Device family
Arria V GZ
Stratix V
Supports Arria V GZ and Stratix V devices.
Number of lanes 1, 2, 4, 8 The total number of duplex lanes
Protocol version
Gen1 (2.5 Gbps)
Gen2 (5.0 Gbps)
Gen3 (8.0 Gbps)
The Gen1 and Gen2 implement the Intel PHY Interface for PCI Express
(PIPE) Architecture PCI Express 2.0 specification. The Gen3
implements the PHY Interface for the PCI Express Architecture PCI
Express 3.0 specification.
Gen1 and Gen2 base data
rate
1 × Lane rate
2 × Lane rate
4 × Lane rate
8 × Lane rate
The base data rate is the output clock frequency of the TX PLL. Select
a base data rate that minimizes the number of PLLs required to
generate all the clocks required for data transmission.
Data rate
2500 Mbps
5000 Mbps
8000 Mbps
Specifies the data rate. This parameter is based on the Protocol
version
you specify. You cannot change it.
Gen1 and Gen2 PLL type
CMU
ATX
You can select either the CMU or ATX PLL. The CMU PLL has a larger
frequency range than the ATX PLL. The ATX PLL is designed to
improve jitter performance and achieves lower channel-to-channel
skew; however, it supports a narrower range of data rates and
reference clock frequencies. Another advantage of the ATX PLL is that
it does not use a transceiver channel, while the CMU PLL does.
Gen3 variants require 2 PLLs for link training which begins in Gen1
and negotiates up to Gen3 if both sides of the link are Gen3 capable.
Gen3 PLL type ATX
Gen3 uses the ATX PLL because its jitter characteristics are better
than the CMU PLL for data rates above 6 Gbps.
PLL reference clock
frequency
100 MHz
125 MHz
You can use either the 100 MHz or 125 MHz input reference clock.
(The PCI Express specifications, require an 100 MHz reference clock.)