User guide

8–4 Chapter 8: PHY IP Core for PCI Express (PIPE)
General Options Parameters
Altera Transceiver PHY IP Core November 2012 Altera Corporation
User Guide
FPGA transceiver width 8, 16, 32
Specifies the width of the interface between the PHY MAC and PHY
(PIPE).The following options are available:
■ Gen1: 8 or 16 bits
■ Gen2: 16 bits
■ Gen3: 32 bits
Using the Gen1 16-bit interface reduces the required clock frequency
by half at the expense of extra FPGA resources.
Run length 5–160
Specifies the maximum number of consecutive 0s or 1s that can
occur in the data stream. The
rx_rlv signal is asserted if the
maximum run length is violated.
Table 8–2. PHY IP Core for PCI Express General Options (Part 2 of 2)
Name Value Description