User guide

Chapter 10: Low Latency PHY IP Core 10–15
Simulation Files and Example Testbench
November 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
Avalon-MM slave interface which connects to the Transceiver Reconfiguration
Controller IP Core. Conversely, you cannot connect the three channels that share an
Avalon-MM interface to different Transceiver Reconfiguration Controller IP Cores.
Doing so causes a Fitter error. For more information, refer to Transceiver
Reconfiguration Controller to PHY IP Connectivity.
Table 10–14 describes the signals in the reconfiguration interface. This interface uses a
clock provided by the reconfiguration controller.
If you are using ×6 or ×N bonding, transceiver dynamic reconfiguration requires that
you assign the starting channel number. Logical channel 0 should be assigned to
either physical transceiver channel 1 or channel 4 of a transceiver bank. However, if
you have already created a PCB with a different lane assignment for logical lane 0,
you can use the workaound shown in Example 10–2 to remove this restriction.
Example 10–2 redefines the
pma_bonding_master parameter using the Quartus II
Assignment Editor. In this example, the
pma_bonding_master was originally assigned
to physical channel 1. (The original assignment could also have been to physical
channel 4.) The
to parameter reassigns the pma_bonding_master to the Low Latency
PHY instance name. You must substitute the instance name from your design for the
instance name shown in quotation marks
Simulation Files and Example Testbench
Refer to Running a Simulation Testbench for a description of the directories and files
that the Quartus II software creates automatically when you generate your Low
Latency PHY IP Core.
f Refer to the Altera wiki for an example testbench that you can use as a starting point
in creating your own verification environment.
Table 10–14. Reconfiguration Interface
Signal Name Direction Description
reconfig_to_xcvr [(<n>70)-1:0] Input
Reconfiguration signals from the Transceiver Reconfiguration
Controller. <n> grows linearly with the number of
reconfiguration interfaces.
reconfig_from_xcvr [(<n>46)-1:0] Output
Reconfiguration signals to the Transceiver Reconfiguration
Controller. <n> grows linearly with the number of
reconfiguration interfaces.
Example 10–2. Overriding Logical Channel 0 Channel Assignment Restrictions in Stratix V Devices for ×6 or ×N Bonding
set_parameter -name pma_bonding_master "\"1\"" -to "<low latency phy
instance>|altera_xcvr_low_latency_phy:my_low_latency_phy_inst|sv_xcvr_low_latency_phy_nr:sv_xcvr_low_l
atency_phy_nr_inst|sv_xcvr_10g_custom_native:sv_xcvr_10g_custom_native_inst|sv_xcvr_native:sv_xcvr_nat
ive_insts[0].gen_bonded_group_native.sv_xcvr_native_inst"