User guide

11–6 Chapter 11: Deterministic Latency PHY IP Core
Delay Estimation Logic
Altera Transceiver PHY IP Core November 2012 Altera Corporation
User Guide
Delay Numbers
Table 11–2 shows the total latency through the TX PCS in parallel clock cycles with the
byte serializer/deserializer turned off. The TX compensation FIFO is in register mode.
Table 11–3 shows the total latency through the RX PCS in parallel clock cycles with the
byte serializer/deserializer turned off. The RX compensation FIFO is in register mode.
Table 11–4 shows the total latency through the TX and RX PMA in UI.
1 There is a small discrepancy between simulation of the delays through the PMA
serializer and deserializer and hardware modeling of these delays.
Table 11–2. TX PCS Total Latency
PCS Datapath Width
TX Phase
Comp FIFO
Serializer 8B/10B Bitslip
Total TX
Parallel
Clock Cycles
Byte Serializer/Deserializer Turned Off
8 bits 1.0 1.0 1.0 0 3.0
16 bits 1.0 1.0 1.0 0 3.0
Byte Serializer/Deserializer Turned On
16 bits 1.0 0.5 0.5 0 2.0
32 bits 1.0 0.5 0.5 0 2.0
Table 11–3. RX PCS Total Latency
PCS Datapath Width
RX Phase
Comp FIFO
Byte
Ordering
Deserializer 8B/10B
Word
Aligner
Total RX
Parallel
Clock
Cycles
Byte Serializer/Deserializer Turned Off
8 bits 1.0 1.0 1.0 1.0 4.0 8.0
16 bits 1.0 1.0 1.0 1.0 5.0 9.0
Byte Serializer/Deserializer Turned On
16 bits 1.0 1.0 1.5 0.5 2.0 6.0
32 bits 1.0 1.0 1.5 0.5 2.5 6.5
Table 11–4. PMA Datapath Total Latency
(1)
Device
TX PMA Latency in UI RX PMA Latency in UI
PCS to PMA Width
10 bits
PCS to PMA Width
with 20 bits
PCS to PMA Width
with 10 bits
PCS to PMA Width
with 20 bits
Arria V 23 43 53 83
Stratix V 13 23 54 84
Note to Table 11–4:
(1) The numbers in this table are from simulation.