User guide

11–12 Chapter 11: Deterministic Latency PHY IP Core
Analog Parameters
Altera Transceiver PHY IP Core November 2012 Altera Corporation
User Guide
Analog Parameters
Click on the appropriate link to specify the analog options for your device:
■ Analog Settings for Arria V Devices
■ Analog Settings for Cyclone V Devices
■ Analog Settings for Stratix V Devices
Number of reference clocks 1–5
Specifies the number of input reference clocks. More than one
reference clock may be required if your design reconfigures channels
to run at multiple frequencies.
Main TX PLL logical index 0–3
Specifies the index for the TX PLL that should be instantiated at
startup. Logical index 0 corresponds to TX PLL0, and so on.
Main TX PLL input clock
source
0–3
Specifies the index for the TX PLL input clock that should be
instantiated at startup. Logical index 0 corresponds to input clock 0
and so on.
CDR PLL input clock source 0–4
Specifies the index for the CDR PLL input clock that should be
instantiated at startup. Logical index 0 corresponds to input clock 0
and so on.
TX PLL (0–3)
(Refer to General Options for a detailed explanation of these parameters.)
PLL Type CMU Specifies the PLL type.
Base data rate
1 × Lane rate
2 × Lane rate
4 × Lane rate
Specifies Base data rate.
Input clock frequency Variable
Specifies the frequency of the PLL input reference clock. The
frequency required is the Base data rate/2. You can use any Input
clock frequency that allows the PLLs to generate this frequency.
Selected input clock source 0–4
Specifies the index of the input clock for this TX PLL. Logical index 0
corresponds to input clock 0 and so on.
Channel Interface
E
nable channel interface On/Off
Turn this option on to enable PLL and datapath dynamic
reconfiguration. When you select this option, the width of
tx_parallel_data and rx_parallel_data buses increases in
the following way:
■ The tx_parallel_data bus is 44 bits per lane; however, only
the low-order number of bits specified by the FPGA fabric
transceiver interface width contain valid data for each lane.
■ The rx_parallel_data bus is 64 bits per lane; however, only
the low-order number of bits specified by the FPGA fabric
transceiver interface width contain valid data.
Table 11–9. PLL Reconfiguration Options
Name Value Description