User guide

11–22 Chapter 11: Deterministic Latency PHY IP Core
Channel Placement and Utilization
Altera Transceiver PHY IP Core November 2012 Altera Corporation
User Guide
Avalon-MM slave interface which connects to the Transceiver Reconfiguration
Controller IP Core. Conversely, you cannot connect the three channels that share an
Avalon-MM interface to different Transceiver Reconfiguration Controller IP Cores.
Doing so causes a Fitter error. For more information, refer to Transceiver
Reconfiguration Controller to PHY IP Connectivity.
Table 11–20 describes the signals in the reconfiguration interface. This interface uses
the Avalon-MM PHY Management interface clock.
Channel Placement and Utilization
The Deterministic Latency PHY IP Core has the following restriction on channel
placement:
■ Channels 0–2 in transceiver banks GXB_L0 and GSB_R0 of Arria V devices are not
available for deterministic latency protocols.
Example 11–1. Informational Messages for the Transceiver Reconfiguration Interface
PHY IP will require 2 reconfiguration interfaces for connection to the external
reconfiguration controller.
Reconfiguration interface offset 0 is connected to the transceiver channel.
Reconfiguration interface offset 1 is connected to the transmit PLL.
Table 11–20. Reconfiguration Interface
Signal Name Direction Description
reconfig_to_xcvr [(<n>70)-1:0] Input
Reconfiguration signals from the Transceiver Reconfiguration
Controller. <n> grows linearly with the number of reconfiguration
interfaces.
reconfig_from_xcvr[(<n>46)-1:0] Output
Reconfiguration signals to the Transceiver Reconfiguration
Controller. <n> grows linearly with the number of reconfiguration
interfaces.