User guide

3–2 Chapter 3: 10GBASE-R PHY IP Core
Altera Transceiver PHY IP Core November 2012 Altera Corporation
User Guide
1 This configuration does not require that all four channels in a quad run the
10GBASE-R protocol.
Figure 3–2. Complete 10GBASE-R PHY Design in Stratix IV GT Device
To MAC
To Embedded
Controller
Avalon-MM
connections
10GBASE-R PHY - Stratix IV Device
SDR XGMII
72 bits @ 156.25 Mbps
To MAC
SDR XGMII
72 bits @ 156.25 Mbps
Avalon-MM
PHY
Management
Bridge
M
S
S
Low Latency
Controller
S
Transceiver
Reconfig
Controller
Alt_PMA
10GBASE-R
10.3 Gbps
10.3125 Gbps serial
To HSSI Pins
PCS
10GBASE-R
(64b/66b)
S
S
Alt_PMA
10GBASE-R
10.3 Gbps
10.3125 Gbps serial
To HSSI Pins
PCS
10GBASE-R
(64b/66b)
S
S