User guide

Chapter 12: Stratix V Transceiver Native PHY IP Core 12–11
Standard PCS Parameters
November 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
Standard PCS Parameters
Figure 12–3 shows the complete datapath and clocking for the Standard PCS. You use
parameters available in the GUI to enable or disable the individual blocks in the
Standard PCS.
f For more information about Standard PCS, refer to the Standard PCS Architecture
section in the Transceiver Architecture in Stratix V Devices.
Figure 12–3. The Standard PCS Datapath
RX Phase
Compensation
FIFO
Byte Ordering
Byte
Deserializer
8B/10B Decoder
Rate Match FIFO
Receiver Standard PCS Receiver PMA
Deskew FIFO
Word Aligner
Deserializer
CDR
Transmitter Standard PCS
Transmitter PMA
Serializer
tx_serial_data
rx_serial_data
FPGA
Fabric
TX Phase
Compensation
FIFO
Byte Serializer
8B/10B Encoder
TX Bit Slip
/2
/2
Parallel Clock
Serial Clock
Parallel and Serial Clock
Clock Divider
Parallel and Serial Clocks (From the ×6 or ×N Clock Lines)
Serial Clock
(From the ×1 Clock Lines)
Central/ Local Clock Divider
Parallel and Serial Clocks
(Only from the Central Clock Divider)
CMU PLL
tx_std_coreclkin
rx_std_coreclkin
rx_std_clkout
tx_std_clkout