User guide

12–26 Chapter 12: Stratix V Transceiver Native PHY IP Core
10G PCS Parameters
Altera Transceiver PHY IP Core November 2012 Altera Corporation
User Guide
Enable rx_10g_frame_sync_err
port
On/Off
When you turn this option On, the 10G PCS includes the
rx_10g_frame_sync_err output port. This signal is asserted to
indicate synchronization control word errors. This signal remains
asserted during the loss of block_lock and does not update until
block_lock is recovered.
Enable rx_10g_frame_skip_ins
port
On/Off
When you turn this option On, the 10G PCS includes the
rx_10g_frame_skip_ins output port. This signal is asserted to
indicate a SKIP word was received by the frame sync in a
non-SKIP word location within the metaframe.
Enable rx_10g_frame_pyld_ins
port
On/Off
When you turn this option On, the 10G PCS includes the
rx_10g_frame_pyld_ins output port. This signal is asserted to
indicate a SKIP word was not received by the frame sync in a
SKIP word location within the metaframe.
Enable rx_10g_frame_skip_err
port
On/Off
When you turn this option On, the 10G PCS includes the
rx_10g_frame_skip_err output port. This signal is asserted to
indicate the frame synchronization has received an erroneous
word in a Skip control word location within the Metaframe. This
signal remains asserted during the loss of block_lock and does
update until block_lock is recovered.
Enable rx_10g_frame_diag_err
port
On/Off
When you turn this option On, the 10G PCS includes the
rx_10g_frame_diag_err output port. This signal is asserted to
indicate a diagnostic control word error. This signal remains
asserted during the loss of block_lock and does update until
block_lock is recovered.
Enable
rx_10g_frame_diag_status port
On/Off
When you turn this option On, the 10G PCS includes the
rx_10g_frame_diag_status 2-bit output port per channel.
This port contains the lane Status Message from the framing
layer Diagnostic Word, bits[33:32]. This message is inserted into
the next Diagnostic Word generated by the frame generation
block.
Table 12–23. Interlaken Frame Synchronizer Parameters (Part 2 of 2)
Parameter Range Description