User guide

Chapter 12: Stratix V Transceiver Native PHY IP Core 12–37
Standard PCS Interface Ports
November 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
Rate Match FIFO
rx_std_rm_fifo_empty
[<n>-1:0]
Output No
Rate match FIFO empty flag. When asserted, the rate
match FIFO is empty. You must synchronize this
signal.
rx_std_rm_fifo_full[<n>-1:0] Output No
Rate match FIFO full flag. When asserted the rate
match FIFO is full. You must synchronize this signal.
Word Aligner
rx_std_bitrev_ena[<n>-1:0] Input No
When asserted, enables bit reversal on the RX
interface. Bit order may be reversed if external
transmission circuitry transmits the most significant
bit first. When enabled, the receive circuitry receives
all words in the reverse order. The bit reversal
circuitry operates on the output of the word aligner.
tx_std_bitslipboundarysel
[5<n>-1:0]
Input No
Bit-Slip boundary selection signal. Specifies the
number of bits that the TX bit slipper must slip.
rx_std_bitslipboundarysel
[5<n>-1:0]
Output No
This signal operates when the word aligner is in
bit-slip word alignment mode. It reports the number
of bits that the RX block slipped to achieve
deterministic latency.
rx_std_runlength_err
[<n>-1:0]
Output No
When asserted, indicates a run length violation.
Asserted if the number of consecutive 1s or 0s
exceeds the number specified in th0e parameter
editor GUI.
rx_st_wa_patternalign Input No
Asserted to enable word alignment in manual word
alignment mode.
rx_std_wa_a1a2size[<n>-1:0] Input No
Used for the SONET protocol. Asserted when the A1
and A2 framing bytes must be detected. A1 and A2
are SONET backplane bytes and are only used when
the PMA data width is 8 bits.
rx_std_bitslip[<n>-1:0] Input No
Used when word aligner mode is bit-slip mode. For
every rising edge of the
rx_std_bitslip signal, the
word boundary is shifted by 1 bit. Each bitslip
removes the earliest received bit from the received
data. You must synchronize this signal.
Table 12–32. Standard PCS Interface Ports (Part 3 of 4)
Name Dir
Synchronous to
tx_std_coreclkin/
rx_std_coreclkin
Description