User guide

12–38 Chapter 12: Stratix V Transceiver Native PHY IP Core
10G PCS Interface
Altera Transceiver PHY IP Core November 2012 Altera Corporation
User Guide
10G PCS Interface
Figure 12–7 illustrates the top-level signals of the 10G PCS. If you enable both the 10G
PCS and Standard PCS your top-level HDL file includes all the interfaces for both.
Miscellaneous
tx_std_elecidle[<n>-1:0] Input No
When asserted, enables a circuit to detect a
downstream receiver. It is used for the PCI Express
protocol. This signal must be driven low when not in
use because it causes the TX PMA to enter electrical
idle mode with the TX serial data signals in tri-state
mode.
rx_std_signaldetect[<n>-1:0] Output No
Signal threshold detect indicator required for the PCI
Express protocol. When asserted, it indicates that the
signal present at the receiver input buffer is above the
programmed signal detection threshold value. You
must synchronize this signal.
Table 12–32. Standard PCS Interface Ports (Part 4 of 4)
Name Dir
Synchronous to
tx_std_coreclkin/
rx_std_coreclkin
Description
Figure 12–7. Stratix V Native PHY 10G PCS Interfaces
Clocks
Frame
Generator
TX FIFO
RX FIFO
Block
Synchronizer
Frame
Synchronizer
Bit-Slip
Gearbox
Feature
64B/66B
BER
10G PCS Interface Ports
CRC32
tx_10g_coreclkin[<n>-1:0]
rx_10g_coreclkin[<n>-1:0]
tx_10g_clkout[<n>-1:0]
rx_10g_clkout[<n>-1:0]
rx_10g_clk33out[<n>-1:0]t
tx_10g_control[8<n>-1:0]
tx_10g_data_valid[<n>-1:0]
tx_10g_fifo_full[<n>-1:0]
tx_10g_fifo_pfull[<n>-1:0]
tx_10g_fifo_empty[<n>-1:0]
tx_10g_fifo_pempt[<n>-1:0]y
tx_10g_fifo_del[<n>-1:0]
tx_10g_fifo_insert[<n>-1:0]
rx_10g_control[10<n>-1:0]
rx_10g_fifo_rd_en[<n>-1:0]
rx_10g_data_valid[<n>-1:0]
rx_10g_fifo_full[<n>-1:0]
rx_10g_fifo_pfull[<n>-1:0]
rx_10g_fifo_empty[<n>-1:0]
rx_10g_fifo_pempty[<n>-1:0]
rx_10g_fifo_align_clr[<n>-1:0]
rx_10g_fifo_align_en[<n>-1:0]
rx_10g_align_val[<n>-1:0]
rx_10g_fifo_del[<n>-1:0]
rx_10g_fifo_insert[<n>-1:0]
rx_10g_crc32err[<n>-1:0]
tx_10g_diag_status[2<n>-1:0]
tx_10g_burst_en[<n>-1:0]
tx_10g_frame[<n>-1:0]
rx_10g_frame[<n>-1:0]
rx_10g_frame_lock[<n>-1:0]
rx_10g_pyld_ins[<n>-1:0]
rx_10g_frame_mfrm_err[<n>-1:0]
rx_10g_frame_sync_err[<n>-1:0]
rx_10g_scr
am_err[<n>-1:0]
rx_10g_frame_skip_ins[<n>-1:0]
rx_10g_frame_skip_err[<n>-1:0]
rx_10g_frame_diag_err[<n>-1:0]
rx_10g_frame_diag_status[2<n>-1:0]
rx_10g_blk_lock[<n>-1:0]
rx_10g_blk_sh_err[<n>-1:0]
rx_10g_bitslip[<n>-1:0]
tx_10g_bitslip[7<n>-1:0]
rx_10g_clr_errblk_count[<n>-1:0]
rx_10g_highber[<n>-1:0]
rx_10g_clr_highber_cnt[<n>-1:0]