User guide

Chapter 12: Stratix V Transceiver Native PHY IP Core 12–45
10G PCS Interface
November 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
rx_10g_frame_skip_err
[<n>-1:0]
Output No
For the Interlaken protocol, asserted to indicate a Skip
Control Word error was received in a Skip Control Word
location within the metaframe.
This signal is sticky during the loss of block lock and
does not update until block lock is re-established. This
signal is pulse-stretched; you must use a synchronizer.
rx_10g_frame_diag_err
[<n>-1:0]
Output No
For the Interlaken protocol, asserted to indicate a
Diagnostic Control Word error was received in a
Diagnostic Control Word location within the metaframe.
This signal is sticky during the loss of block lock and
does not update until block lock is re-established. This
signal is pulse-stretched; you must use a synchronizer.
rx_10g_fram_diag_status
[2<n>-1:0]
outputs No
For the Interlaken protocol, reflects the lane status
message contained in the framing layer Diagnostic
Word (bits[33:32]). This information is latched when a
valid Diagnostic Word is received in a Diagnostic Word
Metaframe location. This signal is pulse-stretched; you
must use a synchronizer.
Block Synchronizer
rx_10g_blk_lock[<n>-1:0] Output No
Active-high status signal that is asserted when block
synchronizer acquires block lock. Valid for the
10GBASE-R and Interlaken protocols, and any basic
mode that uses the lock state machine to achieve and
monitor block synchronization for word alignment.
Once the block synchronizer acquires block lock, it
takes at least 16 errors for
rx_10g_blk_lock to be
deasserted.
rx_10g_blk_sh_err[<n>-1:0] Output No
Error status signal from block synchronizer indicating
an invalid synchronization header has been received.
Valid for the 10GBASE-R and Interlaken protocols, and
any legal basic mode that uses the lock state machine
to achieve and monitor block synchronization for word
alignment. Active only after block lock is achieved. This
signal is pulse-stretched; you must use a synchronizer.
Bit-Slip Gearbox Feature
rx_10g_bitslip[<n>-1:0] Input No
User control bit-slip in the RX Gearbox. Slips one bit per
rising edge pulse.
tx_10g_bitslip[7<n>-1:0] Input No
TX bit-slip is controlled by
tx_bitslip port. s
Shifts the number of bit location specified by
tx_bitslip . The maximum shift is <pcswidth-1>.
64b/66b
rx_10g_clr_errblk_count
[<n>-1:0]
Input No
For the 10GBASE-R protocol, asserted to clear the error
block counter which counts the number of times the RX
state machine enters the RX error state.
Table 12–33. 10G PCS Interface Ports (Part 7 of 8)
Name Dir
Synchronous to
tx_10g_coreclkin/
rx_10g_coreclkin
Description