User guide

13–2 Chapter 13: Arria V Transceiver Native PHY IP Core
Device Family Support
Altera Transceiver PHY IP Core November 2012 Altera Corporation
User Guide
In a typical design, the separately instantiated Transceiver PHY Reset Controller
drives reset signals to Native PHY and receives calibration and locked status signal
from the Native PHY. The Native PHY reconfiguration buses connect the external
Transceiver Reconfiguration Controller for calibration and dynamic reconfiguration
of the channel and PLLs.
You specify the initial configuration when you parameterize the IP core. The
Transceiver Native PHY IP Core connects to the “Transceiver Reconfiguration
Controller IP Core” to dynamically change reference clocks, PLL connectivity, and the
channel configurations at runtime.
Device Family Support
IP cores provide either final or preliminary support for target Altera device families.
These terms have the following definitions:
■ Final support—Verified with final timing models for this device.
■ Preliminary support—Verified with preliminary timing models for this device.
Table 13–1 shows the level of support offered by the Arria V Transceiver Native PHY
IP Core for Altera device families.
Performance and Resource Utilization
Because the Standard PCS and PMA are implemented in hard logic, the Arria V
Native PHY IP Core requires minimal resources.
Parameterizing the Arria V Native PHY
By default, the Arria V Native PHY Transceiver PHY IP defaults to the PMA direct
datapath and an internal PLL. You can change the default configuration to include the
PCS or an external fractional PLL using the MegaWizard Plug-In Manager.
1. For Which device family will you be using?, select Arria V from the list.
2. Click Installed Plug-Ins > Interfaces > Transceiver PHY > Arria V Native PHY
v12.1.
3. Use the tabs on the MegaWizard Plug-In Manager to select the options required
for the protocol.
4. Click Finish to generate your customized Arria V Native PHY IP Core.
1 The Arria V Transceiver Native PHY provides presets for CPRI, GIGE, and the Low
Latency Standard PCS. The presets specify the parameters required to the protocol
specified.
Table 13–1. Device Family Support
Device Family Support
Arria V devices Preliminary
Other device families No support