User guide

13–10 Chapter 13: Arria V Transceiver Native PHY IP Core
Standard PCS Parameters
Altera Transceiver PHY IP Core November 2012 Altera Corporation
User Guide
Byte Ordering Block Parameters
The RX byte ordering block realigns the data coming from the byte deserializer. This
block is necessary when the PCS to FPGA fabric interface width is greater than the
PCS datapath. Because the timing of the RX PCS reset logic is indeterminate, the byte
ordering at the output of the byte deserializer may or may not match the original byte
ordering of the transmitted data. Table 13–12 describes the byte ordering block
parameters.For more information refer to the Byte Ordering section in the Transceiver
Architecture in Arria V Devices.
Enable rx_std_pcfifo_empty port On/Off
When you turn this option On, the RX Phase compensation FIFO
outputs a FIFO empty status flag.
Enable rx_std_rmfifo_empty port On/Off
When you turn this option On, the rate match FIFO outputs a FIFO
empty status flag. The rate match FIFO compensates for small
clock frequency differences between the upstream transmitter
and the local receiver clocks by inserting or removing skip (SKP)
symbols or ordered sets from the inter-packet gap (IPG) or idle
stream.
Enable rx_std_rmfifo_full port On/Off
When you turn this option On, the rate match FIFO outputs a FIFO
full status flag.
Table 13–11. Phase Compensation FIFO Parameters
Parameter Range Description
Table 13–12. Byte Ordering Block Parameters (Part 1 of 2)
Parameter Range Description
Enable RX byte ordering On/Off
When you turn this option On, the PCS includes the byte ordering
block.
Byte ordering control mode
manual
auto
Specifies the control mode for the byte ordering block. The
following modes are available:
■ Manual: Allows you to control the byte ordering block
■ Auto: The word aligner automatically controls the byte
ordering block once word alignment is achieved.
Byte ordering pattern width 8–10
Shows width of the pattern that you must specify. This width
depends upon the PCS width and whether or not 8B/10B
encoding is used as follows:
Width 8B/10B Pad Pattern
8, 16,32 No 8 bits
10,20,40 No 10 bits
8,16,32 Yes 9 bits
Byte ordering symbol count 1–2
Specifies the number of symbols the word aligner should search
for. When the PMA is 16 or 20 bits wide, the byte ordering block
can optionally search for 1 or 2 symbols.
Byte order pattern (hex)
User-specified
8-10 bit pattern
Specifies the search pattern for the byte ordering block.