User guide

Chapter 13: Arria V Transceiver Native PHY IP Core 13–21
SDC Timing Constraints
November 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
■ You can cut these paths in your Synopsys Design Constraints (.sdc) file by using
the
set_false_path command as shown in Example 13–1.
■ You can use the set_max_delay constraint on a given path to create a constraint for
asynchronous signals that do not have a specific clock relationship but require a
maximum path delay. Figure 13–2 illustrates this approach.
■ You can use the set_false path command only during Timequest timing analysis.
Example 13–3 illustrates this approach.
1 In in all of these examples, you must substitute you actual signal names for the signal
names shown.
Example 13–1. Using the set_false_path Constraint to Identify Asynchronous Inputs
set_false_path -through {*10gtxbursten*} -to [get_registers *10g_tx_pcs*SYNC_DATA_REG*]
set_false_path -through {*10gtxdiagstatus*} -to [get_registers
*10g_tx_pcs*SYNC_DATA_REG*]
set_false_path -through {*10gtxwordslip*} -to [get_registers *10g_tx_pcs*SYNC_DATA_REG*]
set_false_path -through {*10gtxbitslip*} -to [get_registers *10g_tx_pcs*SYNC_DATA_REG*]
set_false_path -through {*10grxbitslip*} -to [get_registers *10g_rx_pcs*SYNC_DATA_REG*]
set_false_path -through {*10grxclrbercount*} -to [get_registers
*10g_rx_pcs*SYNC_DATA_REG*]
set_false_path -through {*10grxclrerrblkcnt*} -to [get_registers
*10g_rx_pcs*SYNC_DATA_REG*]
set_false_path -through {*10grxprbserrclr*} -to [get_registers
*10g_rx_pcs*SYNC_DATA_REG*]
set_false_path -through {*8gbitslip*} -to [get_registers *8g_rx_pcs*SYNC_DATA_REG*]
set_false_path -through {*8gbytordpld*} -to [get_registers *8g_rx_pcs*SYNC_DATA_REG*]
set_false_path -through {*8gcmpfifoburst*} -to [get_registers *8g_rx_pcs*SYNC_DATA_REG*]
set_false_path -through {*8gphfifoburstrx*} -to [get_registers
*8g_rx_pcs*SYNC_DATA_REG*]
set_false_path -through {*8gsyncsmen*} -to [get_registers *8g*pcs*SYNC_DATA_REG*]
set_false_path -through {*8gwrdisablerx*} -to [get_registers *8g_rx_pcs*SYNC_DATA_REG*]
set_false_path -through {*rxpolarity*} -to [get_registers *SYNC_DATA_REG*]
set_false_path -through {*pldeidleinfersel*} -to [get_registers *SYNC_DATA_REG*]
Example 13–2. Using the max_delay Constraint to Identify Asynchronous Inputs
# Example: Apply 10ns max delay
set_max_delay -from *tx_from_fifo* -to *8g*pcs*SYNC_DATA_REG1 10
Example 13–3. Using the set_false TimeQuest Constraint to Identify Asynchronous Inputs
#if {$::TimeQuestInfo(nameofexecutable) eq "quartus_fit"} {
#} else {
#set_false_path -from [get_registers {*tx_from_fifo*}] -through {*txbursten*} -to
[get_registers *8g_*_pcs*SYNC_DATA_REG