User guide

November 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
14. Arria V GZ Transceiver Native PHY IP
Core
The Arria V GZTransceiver Native PHY IP Core provides direct access to all control
and status signals of the transceiver channels. Unlike other PHY IP Cores, the Native
PHY IP Core does not include an Avalon Memory-Mapped (Avalon-MM) interface.
Instead, it exposes all signals directly as ports. The Arria V GZ Transceiver Native
PHY IP Core provides the following three datapaths:
■ Standard PCS
■ 10G PCS
■ PMA Direct
You can enable the Standard PCS, the 10G PCS, or both if your design uses the
Transceiver Reconfiguration Controller to change dynamically between the two PCS
datapaths. The transceiver PHY does not include an embedded reset controller. You
can either design custom reset logic or incorporate Altera’s “Transceiver PHY Reset
Controller IP Core” to implement reset functionality. The Native Transceiver PHY’s
primary use in Arria V GT devices for data rates greater than 6.5536 Gbps.
In PMA Direct mode, the Native PHY provides direct access to the PMA from the
FPGA fabric; consequently, the latency for transmitted and received data is very low.
However, you must implement any PCS function that your design requires in the
FPGA fabric.