User guide

14–2 Chapter 14: Arria V GZ Transceiver Native PHY IP Core
Device Family Support
Altera Transceiver PHY IP Core November 2012 Altera Corporation
User Guide
Figure 14–1 illustrates the use of the Arria V GZ Transceiver Native PHY IP Core. As
this figure illustrates, TX PLL and clock data recovery (CDR) reference clocks from the
pins of the device are input to the PLL module and CDR logic. When enabled, the 10G
or Standard PCS drives TX parallel data and receives RX parallel data. When neither
PCS is enabled the Native PHY operates in PMA Direct mode.
In a typical design, the separately instantiated Transceiver PHY Reset Controller
drives reset signals to Native PHY and receives calibration and locked status signal
from the Native PHY. The Native PHY reconfiguration buses connect the external
Transceiver Reconfiguration Controller for calibration and dynamic reconfiguration
of the PLLs.
You specify the initial configuration when you parameterize the IP core. The
Transceiver Native PHY IP Core connects to the “Transceiver Reconfiguration
Controller IP Core” to dynamically change reference clocks and PLL connectivity at
runtime.
Device Family Support
IP cores provide either final or preliminary support for target Altera device families.
These terms have the following definitions:
■ Final support—Verified with final timing models for this device.
■ Preliminary support—Verified with preliminary timing models for this device.
Figure 14–1. Arria V GZ Native Transceiver PHY IP Core
PLLs
PMA
altera_xcvr_native_<dev>
Transceiver Native PHY
Transceiver
Reconfiguration
Controller
Reconfiguration to XCVR
Reconfiguration from XCVR
TX and RX Resets
Calilbration Busy
PLL and RX Locked
RX PCS Parallel Data
TX PCS Parallel Data
CDR Reference Clock
(when neither PCS is enabled)
TX PLL Reference Clock
Serializer/
Clock
Generation
Block
RX Serial Data
to
FPGA fabric
Transceiver
PHY Reset
Controller
TX PMA Parallel Data
RX PMA Parallel Data
TX Serial Data
Serializer
Deserializer
Standard
PCS
(optional)
10G PCS
(optional)