User guide

Chapter 14: Arria V GZ Transceiver Native PHY IP Core 14–3
Performance and Resource Utilization
November 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
Table 14–1 shows the level of support offered by the Arria V GZ Transceiver Native
PHY IP Core for Altera device families.
Performance and Resource Utilization
Because the 10G PCS, Standard PCS, and PMA are implemented in hard logic, the
Arria V GZ Native PHY IP Core uses less than 1% of the available ALMs, memory,
primary and secondary logic registers.
Parameter Presets
Presets allow you to specify a group of parameters to implement a particular protocol
or application. If you apply a preset, the parameters with specific required values are
set for you. When applied, the preset is in boldface and remains as such unless you
change some of the preset parameters. Selecting a preset does not prevent you from
changing any parameter to meet the requirements of your design. Figure 14–2
illustrates the Preset panel and form to create custom presets.
Table 14–1. Device Family Support
Device Family Support
Arria V GZ devices Preliminary
Other device families No support
Figure 14–2. Preset Panel and Form To Create Custom Presets