User guide

Chapter 14: Arria V GZ Transceiver Native PHY IP Core 14–9
PMA Parameters
November 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
Table 14–8 lists the best case latency for the most significant bit of a word for the RX
deserializer. For example, for an 8-bit interface width, the latencies in UI are 11 for bit
7, 12 for bit 6, 13 for bit 5, and so on.
Table 14–9 lists the best- case latency for the LSB of the TX serializer for all supported
interface widths for the PMA Direct datapath.
Table 14–9 lists the best- case latency for the LSB of the TX serializer for all supported
interface widths.
40 bits 43
64 bits 99
80 bits 123
Table 14–8. Latency for RX Deserialization in Arria V GZ Devices
FPGA Fabric Interface Width Arria V Latency in UI
8 bits 19
10 bits 23
16 bits 35
20 bits 43
80 bits 123
Table 14–9. Latency for TX Serialization in Arria V GZ Devices
FPGA Fabric Interface Width Arria V GZ Latency in UI
8 bits 44
10 bits 54
16 bits 68
20 bits 84
32 bits 100
40 bits 124
64 bits 132
80 bits 164
Table 14–10. Latency for TX Serialization n Arria V GZ Devices
FPGA Fabric Interface Width Arria V Latency in UI
8 bits 43
10 bits 53
16 bits 67
20 bits 83
80 bits 163
Table 14–7. Latency for RX Deserialization in Arria V GZ Devices (Part 2 of 2)
FPGA Fabric Interface Width Arria V GZ Latency in UI