User guide

14–14 Chapter 14: Arria V GZ Transceiver Native PHY IP Core
Standard PCS Parameters
Altera Transceiver PHY IP Core November 2012 Altera Corporation
User Guide
f For more information refer to the Byte Ordering section in the Transceiver Architecture in
Arria V Devices.
Table 14–14. Byte Ordering Block Parameters
Parameter Range Description
Enable RX byte ordering On/Off
When you turn this option On, the PCS includes the byte ordering
block.
Byte ordering control mode
manual
auto
Specifies the control mode for the byte ordering block. The
following modes are available:
■ Manual: Allows you to control the byte ordering block
■ Auto: The word aligner automatically controls the byte
ordering block once word alignment is achieved.
Byte ordering pattern width 8–10
Shows width of the pad that you must specify. This width
depends upon the PCS width and whether nor not 8B/10B
encoding is used as follows:
Width 8B/10B Pad Pattern
8/16,32 No 8 bits
10,20,40 No 10 bits
8,16,32 Yes 9 bits
Byte ordering symbol count 1–2
Specifies the number of symbols the word aligner should search
for. When the PMA is 16 or 20 bits wide, the byte ordering block
can optionally search for 1 or 2 symbols.
Byte order pattern (hex)
User-specified
8-10 bit pattern
Specifies the search pattern for the byte ordering block.
Byte order pad value (hex)
User–specified
8-10 bit pattern
Specifies the pad pattern that is inserted by the byte ordering
block. This value is inserted when the byte order pattern is
recognized.
The byte ordering pattern should occupy the least significant byte
(LSB) of the parallel TX data. If the byte ordering block identifies
the programmed byte ordering pattern in the most significant
byte (MSB) of the byte-deserialized data, it inserts the appropriate
number of user-specified pad bytes to push the byte ordering
pattern to the LSB position, restoring proper byte ordering.
Enable rx_std_byteorder_ena
port
On/Off
Enables the optional
rx_std_byte_order_ena control input
port. When this signal is asserted, the byte ordering block
initiates a byte ordering operation if the Byte ordering control
mode is set to manual. Once byte ordering has occurred, you
must deassert and reassert this signal to perform another byte
ordering operation. This signal is an synchronous input signal;
however, it must be asserted for at least 1 cycle of
rx_std_clkout .
Enable rx_std_byteorder_flag
port
On/Off
Enables the optional
rx_std_byteorder_flag status output
port. When asserted, indicates that the byte ordering block has
performed a byte order operation. This signal is asserted on the
clock cycle in which byte ordering occurred. This signal is
synchronous to the
rx_std_clkout clock.