User guide

14–16 Chapter 14: Arria V GZ Transceiver Native PHY IP Core
Standard PCS Parameters
Altera Transceiver PHY IP Core November 2012 Altera Corporation
User Guide
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Word Aligner and Bit-Slip Parameters
The word aligner aligns the data coming from RX PMA deserializer to a given word
boundary. When the word aligner operates in bit-slip mode, the word aligner slips a
single bit for every rising edge of the bit slip control signal.Table 14–18 describes the
word aligner and bit-slip parameters.
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Table 14–17. Rate Match FIFO Parameters
Parameter Range Description
Enable RX rate match FIFO On/Off
When you turn this option On, the PCS includes a FIFO to
compensate for the very small frequency differences between the
local system clock and the RX recovered clock.
RX rate match insert/delete +ve
pattern (hex)
User-specified
20 bit pattern
Specifies the +ve (positive) disparity value for the RX rate match
FIFO as a hexadecimal string.
RX rate match insert/delete -ve
pattern (hex)
User-specified
20 bit pattern
Specifies the -ve (negative) disparity value for the RX rate match
FIFO as a hexadecimal string.
Enable rx_std_rm_fifo_empty
port
On/Off
When you turn this option On, the rate match FIFO outputs a FIFO
empty status flag. The rate match FIFO compensates for small
clock frequency differences between the upstream transmitter
and the local receiver clocks by inserting or removing skip (SKP)
symbols or ordered sets from the inter-packet gap (IPG) or idle
stream.
Enable rx_std_rm_fifo_full port On/Off
When you turn this option On, the rate match FIFO outputs a FIFO
full status flag.
Table 14–18. Word Aligner and Bit-Slip Parameters (Part 1 of 2)
Parameter Range Description
Enable TX bit-slip On/Off
When you turn this option On, the PCS includes the bit-slip
function. The outgoing TX data can be slipped by the number of
bits specified by the
tx_bitslipboundarysel control signal.
Enable
tx_std_bitslipboundarysel
control input port.
On/Off
When you turn this option On, the PCS includes the optional
tx_std_bitslipboundarysel control input port.
RX word aligner mode
bit_silp
sync_sm
manual
Specifies one of the following 3 modes for the word aligner:
■ Bit_slip: You can use bit slip mode to shift the word boundary.
For every rising edge of the
rx_bitslip signal, the word
boundary is shifted by 1 bit. Each bit-slip removes the earliest
received bit from the received data
■ Sync_sm: In synchronous state machine mode, a
programmable state machine controls word alignment. You
can only use this mode with 8B/10B encoding. The data width
at the word aligner can be 10 or 20 bits
■ Manual: This mode Enables word alignment by asserting the
rx_std_wa_patternalign . This is an edge sensitive signal.