User guide

14–18 Chapter 14: Arria V GZ Transceiver Native PHY IP Core
Standard PCS Parameters
Altera Transceiver PHY IP Core November 2012 Altera Corporation
User Guide
Enable TX polarity inversion On/Off
When you turn this option On, the
tx_std_polinv port controls
polarity inversion of TX parallel data before transmitting the
parallel data to the PMA.
Enable RX polarity inversion On/Off
When you turn this option On, asserting
rx_std_polinv
controls polarity inversion of RX parallel data after PMA
transmission.
Enable rx_std_bitrev_ena port On/Off
When you turn this option On, asserting
rx_std_bitrev_ena
control port causes the RX data order to be reversed from the
normal order, LSB to MSB, to the opposite, MSB to LSB. This
signal is an asynchronous input.
Enable rx_std_byterev_ena port On/Off
When you turn this option On, asserting
rx_std_byterev_ena
input control port causes swaps the order of the individual 8- or
10-bit words received from the PMA.
Enable tx_std_polinv port On/Off
When you turn this option On, the
tx_std_polinv input is
enabled. You can use this control port to swap the positive and
negative signals of a serial differential link if they were
erroneously swapped during board layout.
Enable rx_std_polinv port On/Off
When you turn this option On, the
rx_std_polinv input is
enabled. You can use this control port to swap the positive and
negative signals of a serial differential link if they were
erroneously swapped during board layout.
Enable tx_std_elecidle port On/Off
When you turn this option On, the
tx_std_elecidle input port
is enabled. When this signal is asserted, it forces the transmitter
to electrical idle. This signal is required for the PCI Express
protocol.
Enable rx_std_signaldetect port On/Off
When you turn this option On, the optional
tx_std_signaldetect output port is enabled. This signal is
required for the PCI Express protocol. If enabled, the signal
threshold detection circuitry senses whether the signal level
present at the RX input buffer is above the signal detect threshold
voltage that you specified.
Table 14–19. Bit Reversal and Polarity Inversion Parameters (Part 2 of 2)
Parameter Range Description