User guide

Chapter 3: 10GBASE-R PHY IP Core 3–11
Data Interfaces
November 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
Data Interfaces
Table 3–10 describes the signals in the SDR XGMII TX and RX interface. The TX
signals are driven from the MAC to the PCS. The RX signals are driven from the PCS
to the MAC.
Table 3–10. SDR XGMII TX Inputs (Part 1 of 2)
Signal Name Direction Description
XGMII TX Interface
xgmii_tx_dc_[<n>71:0] Input
Contains 8 lanes of data and control for XGMII. Each lane consists of 8 bits of
data and 1 bit of control.
■ Lane 0–[7:0]/[8]
■ Lane 1–[16:9]/[17]
■ Lane 2–[25:18]/[26]
■ Lane 3–[34:27]/[35]
■ Lane 4–[43:36]/[44]
■ Lane 5–[52:45]/[53]
■ Lane 6–[61:54]/[62]
■ Lane 7–[70:63]/[71]
Refer to Table 3–11 for the mapping of the
xgmii_tx_dc data and control to the
xgmii_sdr_data and xgmii_sdr_ctrl signals.
■
tx_ready Output
Asserted when the TX channel is ready to transmit data. Because the
readyLatency on this Avalon-ST interface is 0, the MAC may drive tx_ready as
soon as it comes out of reset.
xgmii_tx_clk Input The XGMII TX clock which runs at 156.25 MHz.
XGMII RX Interface
xgmii_rx_dc_<n>[71:0] Output
Contains 8 lanes of data and control for XGMII. Each lane consists of 8 bits of
data and 1 bit of control.
■ Lane 0–[7:0]/[8]
■ Lane 1–[16:9]/[17]
■ Lane 2–[25:18]/[26]
■ Lane 3–[34:27]/[35]
■ Lane 4–[43:36]/[44]
■ Lane 5–[52:45]/[53]
■ Lane 6–[61:54]/[62]
■ Lane 7–[70:63]/[71]
Refer to Table 3–12 for the mapping of the
xgmii_rx_dc data and control to the
xgmii_sdr_data and xgmii_sdr_ctrl signals.
rx_ready Output Asserted when the RX reset is complete.