User guide

Chapter 14: Arria V GZ Transceiver Native PHY IP Core 14–23
10G PCS Parameters
November 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
Enable rx_10g_fifo_data_valid
port
On/Off
When you turn this option On, the 10G PCS includes the
rx_data_valid signal which Indicates when rx_data is valid.
This option is available when you select the following parameters:
■ 10G PCS protocol mode is Interlaken
■ 10G PCS protocol mode is Basic and RX FIFO mode is
phase_comp
■ 10G PCS protocol mode is Basic and RX FIFO mode is
register
Enable rx_10g_fifo_full port On/Off
When you turn this option On, the 10G PCS includes the active
high
rx_10g_fifo_full port. rx_10g_fifo_full is
synchronous to
rx_clkout .
Enable rx_10g_fifo_pfull port On/Off
When you turn this option On, the 10G PCS includes the active
high
rx_10g_fifo_pfull port. rx_10g_fifo_pfull is
synchronous to
rx_clkout .
Enable rx_10g_fifo_empty port On/Off
When you turn this option On, the 10G PCS includes the active
high
rx_10g_fifo_empty port.
Enable rx_10g_fifo_pempty port On/Off
When you turn this option On, the 10G PCS includes the
rx_10g_fifo_pempty port.
Enable rx_10g_fifo_del port
(10GBASE-R)
On/Off
When you turn this option On, the 10G PCS includes the
rx_10g_fifo_del port. This signal is asserted when a word is
deleted from the RX FIFO. This signal is only used for the
10GBASE-R protocol.
Enable rx_10g_fifo_insert port
(10GBASE-R)
On/Off
When you turn this option On, the 10G PCS includes the
rx_10g_fifo_insert port. This signal is asserted when a word
is inserted into the RX FIFO. This signal is only used for the
10GBASE-R protocol.
Enable rx_10g_fifo_rd_en port
(Interlaken)
On/Off
When you turn this option On, the 10G PCS includes the
rx_10g_fifo_rd_en input port. Asserting this signal reads a
word from the RX FIFO. This signal is only available for the
Interlaken protocol.
Enable rx_10g_fifo_align_val
port (Interlaken)
On/Off
When you turn this option On, the 10G PCS includes the
rx_10g_fifo_align_val output port. This signal is asserted
when the word alignment pattern is found. This signal is only
available for the Interlaken protocol.
Enable rx_10g_fifo_align_clr
port (Interlaken)
On/Off
When you turn this option On, the 10G PCS includes the
rx_10g_fifo_align_clr input port. When this signal is
asserted, the FIFO resets and begins searching for a new
alignment pattern. This signal is only available for the Interlaken
protocol.
Enable rx_10g_fifo_align_en
port (Interlaken)
On/Off
When you turn this option On, the 10G PCS includes the
rx_10g_fifo_align_en input port. This signal is used for FIFO
deskew for Interlaken. When asserted, the corresponding channel
is enabled for alignment. This signal is only available for the
Interlaken protocol.
Table 14–22. 10G RX FIFO Parameters (Part 2 of 2)
Parameter Range Description