User guide

Chapter 14: Arria V GZ Transceiver Native PHY IP Core 14–45
Dynamic Reconfiguration
November 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
■ You can use the set_max_delay constraint on a given path to create a constraint for
asynchronous signals that do not have a specific clock relationship but require a
maximum path delay. Example 14–2 illustrates this approach.
■ You can use the set_false path command only during Timequest timing analysis.
Example 14–3 illustrates this approach.
1 In in all of these examples, you must substitute you actual signal names for the signal
names shown.
Dynamic Reconfiguration
As silicon progresses towards smaller process nodes, circuit performance is affected
more by variations due to process, voltage, and temperature (PVT). These process
variations result in analog voltages that can be offset from required ranges. The
calibration performed by the dynamic reconfiguration interface compensates for
variations due to PVT.
For non-bonded clocks, each channel and each TX PLL has a separate dynamic
reconfiguration interfaces. The MegaWizard Plug-In Manager provides informational
messages on the connectivity of these interfaces. Example 14–4 shows the messages
for the Arria V GZ Native PHY with four duplex channels, four TX PLLs, in a
non-bonded configuration.
For more information about transceiver reconfiguration refer to Chapter 16,
Transceiver Reconfiguration Controller IP Core.
If you are using ×6 or ×N bonding, transceiver dynamic reconfiguration requires that
you assign the starting channel number. Logical channel 0 should be assigned to
either physical transceiver channel 1 or channel 4 of a transceiver bank. However, if
you have already created a PCB with a different lane assignment for logical lane 0,
you can use the workaound shown in Example 14–5 to remove this restriction.
Example 14–5 redefines the
pma_bonding_master parameter using the Quartus II
Example 14–2. Using the mandala Constraint to Identify Asynchronous Inputs
# Example: Apply 10ns max delay
set_max_delay -from *tx_from_fifo* -to *8g*pcs*SYNC_DATA_REG1 10
Example 14–3. Using the set_false TimeQuest Constraint to Identify Asynchronous Inputs
#if {$::TimeQuestInfo(nameofexecutable) eq "quartus_fit"} {
#} else {
#set_false_path -from [get_registers {*tx_from_fifo*}] -through {*txbursten*} -to
[get_registers *8g_*_pcs*SYNC_DATA_REG
Example 14–4. Informational Messages for the Transceiver Reconfiguration Interface
PHY IP will require 8 reconfiguration interfaces for connection to the external
reconfiguration controller.
Reconfiguration interface offsets 0-3 are connected to the transceiver channels.
Reconfiguration interface offsets 4–7 are connected to the transmit PLLs.