User guide

Chapter 15: Cyclone V Transceiver Native PHY IP Core 15–17
Common Interface Ports
November 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
tx_pll_refclk[<r>-1:0] Input The reference clock input to the TX PLL.
rx_pma_clkout[<n>-1:0] Output RX parallel clock (recovered clock) output from PMA
rx_clklow[<n>-1:0] Output
The RX parallel recovered clock input to the phase frequency
detector (PFD). When operating CDR in manual lock mode, you
can use this clock as an input with
rx_fref to an external PPM
detector.
rx_fref[<n>-1:0] Output
The RX local reference lock input to the PFD. When operating
CDR in manual lock mode, you can use this clock with
rx_clklow as an input to an external PPM detector.
rx_cdr_refclk[<n>-1:0] Input Input reference clock for the RX PFD circuit.
Resets
pll_powerdown[<p>-1:0] Input
When asserted, resets the TX PLL. Active high, edge sensitive
reset signal.
tx_analogreset[<n>-1:0] Input
When asserted, resets for TX PMA, TX clock generation block,
and serializer. Active high, edge sensitive reset signal.
tx_digitalreset[<n>-1:0] Input
When asserted, resets the digital components of the TX datapath.
Active high, edge sensitive, asynchronous reset signal. If your
design includes bonded TX PCS channels, refer to Timing
Constraints for Reset Signals when Using Bonded PCS Channels
for a SDC constraint you must include in your design.
rx_analogreset[<n>-1:0] Input
When asserted, resets the RX CDR, deserializer. Active high, edge
sensitive, asynchronous reset signal.
rx_digitalreset[<n>-1:0] Input
When asserted, resets the digital components of the RX datapath.
Active high, edge sensitive, asynchronous reset signal.
Parallel data ports
tx_parallel_data[43:0] Input
PCS TX parallel data. Used when you enable the Standard
datapath.
rx_parallel_data[63:0] Output
PCS RX parallel data. Used when you enable the Standard
datapath.
TX and RX serial ports
tx_serial_data[<n>-1:0] Output TX differential serial output data.
rx_serial_data[<n>-1:0] Input RX differential serial output data.
Control and Status ports
rx_seriallpbken[<n>-1:0] Input
When asserted, the transceiver enters serial loopback mode.
Loopback drives serial TX data to the RX interface.
rx_set_locktodata[<n>-1:0] Input
When asserted, programs the RX CDR to manual lock to data
mode in which you control the reset sequence using the
rx_set_locktoref and rx_set_locktodata . Refer to
“Transceiver Reset Sequence” inTransceiver Reset Control and
Power-Down in Cyclone V Devices for more information about
manual control of the reset sequence.
Table 15–18. Native PHY Common Interfaces (Part 2 of 3)
Name Direction Description