User guide

November 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
16. Transceiver Reconfiguration
Controller IP Core
The Altera Transceiver Reconfiguration Controller dynamically reconfigures analog
settings in Arria V, Cyclone V, and Stratix V devices. Reconfiguration allows you to
compensate for variations due to process, voltage, and temperature (PVT) in 28-nm
devices. It is required for Arria V, Cyclone V, and Stratix V devices that include
transceivers. The reconfiguration functionality available in Arria V and Cyclone V
devices is a subset of the functionality available for Stratix V devices. Table 16–1
summarizes the features available for all 28-nm devices.
1 Some of the reconfiguration features not available for Arria V and Cyclone V devices
in the current release, may be available in subsequent releases. Arria V and Cyclone V
devices do not include ATX PLLs. Stratix V and Arria V GZ devices include ATX
PLLs.
f For more information about the features that are available for each device refer to the
following device documentation: Dynamic Reconfiguration in Stratix V Devices,
Dynamic Reconfiguration in Arria V Devices, and Dynamic Reconfiguration in Cyclone V
Devices. These chapters are included in the Stratix V, Arria V, and Cyclone V device
handbooks, respectively.
Table 16–1. Device Support for Dynamic Reconfiguration
Area Feature Stratix V Arria V Arria V GZ Cyclone V
Calibration Functions
Offset cancellation vvvv
Duty cycle distortion calibration vvv—
ATX PLL calibration v — v —
Analog Features
On-chip signal quality monitoring v — v —
Decision feedback equalization (DFE) v — v —
Adaptive equalization v — v —
Loopback modes
Pre-CDR reverse serial loopback vvvv
Post-CDR reverse serial loopback vvvv
PLL reconfiguration
Reference clock switching (CDR, ATX PLLs,
and TX PLLs)
vvvv
TX PLL connected to a transceiver channel
reconfiguration
vvvv
Transceiver
Channel/PLL
Reconfiguration
RX CDR reconfiguration vvvv
Reconfiguration of PCS blocks vvvv
TX PLL switching v — v —
ATX PLL switching v — v —
TX local clock divider reconfiguration (1,2,4,8) vvvv
FPGA fabric-transceiver channel data width
reconfiguration
vvvv