User guide

3–16 Chapter 3: 10GBASE-R PHY IP Core
Clocks for Stratix IV Devices
Altera Transceiver PHY IP Core November 2012 Altera Corporation
User Guide
The PCS runs at 257.8125 MHz using the pma_rx_clock provided by the PMA. You
must provide the PMA an input reference clock running at 644.53725 MHz to generate
the 257.8125 MHz clock. Figure 3–9 illustrates the clock generation and distribution
for Stratix IV devices.
Figure 3–9. Stratix IV GT Clock Generation and Distribution
pll_ref_clk
644.53125 MHz
10.3125
Gbps serial
516.625
MHz
257.8125
MHz
516.625
MHz
257.8125
MHz
156.25 MHz
10GBASE-R Transceiver Channel - Stratix IV GT
TX
RX
TX PCS
(hard IP)
TX PCS
(soft IP)
2040
64-bit data, 8-bit control
64-bit data, 8-bit control
TX PMA
/2
10.3125
Gbps serial
RX PCS
(hard IP)
RX PCS
(soft IP)
2040
RX PMA
/2
5/4
TX PLL
8/33
GPLL
xgmii_rx_clk
xgmii_tx_clk