User guide

Chapter 16: Transceiver Reconfiguration Controller IP Core 16–5
Performance and Resource Utilization
November 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
Performance and Resource Utilization
Table 16–4 shows the approximate device resource utilization for a the Transceiver
Reconfiguration Controller for Stratix V devices. The numbers of combinational
ALUTs and logic registers are rounded to the nearest 50. Table 16–4 also shows the
time required for calibration and AEQ functions.
1 To close timing, you may need to instantiate multiple instances of the Transceiver
Reconfiguration Controller IP Core to reduce routing delays.
Parameterizing the Transceiver Reconfiguration Controller IP Core in
the MegaWizard Plug-In Manager
Complete the following steps to configure the Transceiver Reconfiguration Controller
IP Core in the MegaWizard Plug-In Manager:
1. For Which device family will you be using?, select Arria V, Arria V GZ,
Cyclone V, or Stratix V from the list.
2. Click Installed Plug-Ins > Interfaces > Transceiver PHY >Transceiver
Reconfiguration Controller v12.1.
3. Select the options required for your design. For a description of these options, refer
to the General Options Parameters.
Stratix V devices Preliminary
Other device families No support
Table 16–3. Device Family Support (Part 2 of 2)
Device Family Support
Table 16–4. Resource Utilization for Stratix V Devices
Component ALUTs Registers
Memory
Blocks
M20Ks Run Time
Transceiver Calibration Functions
Offset Cancellation 500 400 0 0 100
s/channel
Duty cycle calibration 350 400 0 0 70
s/channel
ATX PLL calibration 650 450 0 4 60
s/channel
Analog Features
EyeQ 300 200 0 0 —
AEQ 700 500 0 0 40
s/channel
Reconfiguration Features
Channel and PLL reconfiguration 400 500 0 0 —
(1)
PLL reconfiguration (only) 250 350 0 0 —
(1)
Note to Table 16–4:
(1) The time to complete these functions depends upon the complexity of the reconfiguration operation.