User guide

Chapter 16: Transceiver Reconfiguration Controller IP Core 16–9
Interfaces
November 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
Transceiver Reconfiguration Interface
Table 16–7 describes the signals that comprise the dynamic reconfiguration interface.
The Transceiver Reconfiguration Controller communicates with the PHY IP cores
using this interface. In Table 16–7, <n> is the number of reconfiguration interfaces
connected to the Transceiver Reconfiguration Controller.
reconfig_mif_waitrequest Input
When asserted, indicates that the MIF Avalon-MM slave is not
ready to respond to a read request.
cal_busy_in Input
In Arria V devices, acts as a status port for DCD calibration to
prevent simultaneous DCD calibration for multiple channels
on the same side of the device. This signal is only available
when you select Create optional calibration status ports.
If your design includes more than 1 Transceiver
Reconfiguration Controller on the same side of the FPGA, you
must daisy chain the
tx_cal_busy output ports to the
cal_busy_in input ports on the same side of the FPGA. Arria
V devices require DCD calibration for channels with data rates
 4.9152 Gbps.
Table 16–6. MIF Reconfiguration Management Avalon-MM Master Interface (Part 2 of 2)
Signal Name Direction Description
Table 16–7. Transceiver Reconfiguration Interface (Part 1 of 2)
Signal Name Direction Description
reconfig_to_xcvr[(<n>×70)-1:0] Output
Parallel reconfiguration bus from the Transceiver
Reconfiguration Controller to the PHY IP Core.
reconfig_from_xcvr[(<n>×46)-1:0] Input
Parallel reconfiguration bus from the PHY IP core to the
Transceiver Reconfiguration Controller.
reconfig_busy Output
When asserted, indicates that a reconfiguration operation is in
progress and no further reconfiguration operations should be
performed. You can monitor this signal to determine the
status of the Transceiver Reconfiguration Controller.
Alternatively, you can monitor the
busy bit of the control
and
status registers of any reconfiguration feature to
determine the status of the Transceiver Reconfiguration
Controller.