User guide

Chapter 16: Transceiver Reconfiguration Controller IP Core 16–11
Transceiver Reconfiguration Controller Memory Map
November 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
Transceiver Reconfiguration Controller Memory Map
Each register-based feature has its own Avalon-MM address space within the
Transceiver Reconfiguration Controller as Figure 16–3 illustrates.
reconfig_mgmt_readdata[31:0] Output Output data.
reconfig_mgmt_write Input Write signal. Active high.
reconfig_mgmt_read Input Read signal. Active high.
Table 16–8. Reconfiguration Management Interface (Part 2 of 2)
Signal Name Direction Description
Figure 16–3. Memory Map of the Transceiver Reconfiguration Controller Registers
Direct Addressing
Address Offset
0x00
0x13
0x0B
0x1B
0x2B
0x33
0x3B
0x43
0x7F
Transceiver Reconfiguration Controller
Avalon-MM Interface
reconfig_mgmt_*
Avalon-MM
Registers
Signal Integrity
Features
DFE
ADCE
AT X
Tuning
MIF
Streamer
PLL
Reconfig
EyeQ
PMA
Analog
EyeQ
. . .
DFE
. . .
PMA
ADCE
. . .
AT X
. . .
Streamer
. . .
PLL
. . .
SM
Embedded
Controller
. . .