User guide

Chapter 16: Transceiver Reconfiguration Controller IP Core 16–29
Streamer Module Registers
November 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
Table 16–24 lists the internal Streamer Module registers that you access to control and
determine the status of a MIF operation.
7’h3B [15:0] RW streamer offset
When the MIF mode = 2’b00, the offset register specifies a
an internal MIF Streamer register. Refer to Table 16–24 for
definitions of these registers. When
MIF Mode = 2’b01,
offset register specifies register in the transceiver
7’h3C [31:0] RW
data
When the MIF Mode = 2’b00, the data register stores read
or write data for indirect access to the location specified in
the
offset register. When MIF Mode = 2’b01, data holds an
update for transceiver to be dynamically reconfigured.
Table 16–23. Streamer Module Registers (Part 2 of 2)
PHY
Addr
Bits R/W Register Name Description